CZ

Christian Zistl

AM AMD: 11 patents #1,098 of 9,279Top 15%
Globalfoundries: 2 patents #1,397 of 4,424Top 35%
📍 Dresden, TX: #4 of 9 inventorsTop 45%
Overall (All Time): #384,312 of 4,157,543Top 10%
13
Patents All Time

Issued Patents All Time

Showing 1–13 of 13 patents

Patent #TitleCo-InventorsDate
8698312 Semiconductor device including a hybrid metallization layer stack for enhanced mechanical strength during and after packaging James Werking, Frank Feustel, Peter Huebler 2014-04-15
7737021 Resist trim process to define small openings in dielectric layers Srikanteswara Dakshina-Murthy, Paul R. Besser, Jonathan B. Smith, Eric M. Apelgren, Jeremy I. Martin +2 more 2010-06-15
7416992 Method of patterning a low-k dielectric using a hard mask Matthias Lehr, Peter Huebler 2008-08-26
7005380 Simultaneous formation of device and backside contacts on wafers having a buried insulator layer Massud Aminpur, Gert Burbach 2006-02-28
6881665 Depth of focus (DOF) for trench-first-via-last (TFVL) damascene processing with hard mask and low viscosity photoresist Ting Tsui, Stephen Keetai Park 2005-04-19
6806191 Semiconductor device with a copper line having an increased resistance against electromigration and a method of forming the same Jörg Hohage, Hartmut Rülke, Peter Hübler 2004-10-19
6610594 Locally increasing sidewall density by ion implantation Eric M. Apelgren, Jeremy I. Martin, Paul R. Besser, Fred Cheung 2003-08-26
6514844 Sidewall treatment for low dielectric constant (low K) materials by ion implantation Jeremy I. Martin, Eric M. Apelgren, Paul R. Besser, Srikantewara Dakshina-Murthy, Jonathan B. Smith +2 more 2003-02-04
6500755 Resist trim process to define small openings in dielectric layers Srikanteswara Dakshina-Murthy, Paul R. Besser, Jonathan B. Smith, Eric M. Apelgren, Jeremy I. Martin +2 more 2002-12-31
6406993 Method of defining small openings in dielectric layers Srikanteswara Dakshina-Murthy, Paul R. Besser, Jonathan B. Smith, Eric M. Apelgren, Jeremy I. Martin +2 more 2002-06-18
6313538 Semiconductor device with partial passivation layer Paul R. Besser, Eric M. Apelgren, Nicholas J. Kepler, Srikanteswara Dakshina-Murthy 2001-11-06
6268255 Method of forming a semiconductor device with metal silicide regions Paul R. Besser, Nicholas J. Kepler 2001-07-31
6261963 Reverse electroplating of barrier metal layer to improve electromigration performance in copper interconnect devices Larry Zhao, Paul R. Besser, Eric M. Apelgren, Jonathan B. Smith 2001-07-17