GK

George J. Kluth

AM AMD: 9 patents #1,329 of 9,279Top 15%
Globalfoundries: 2 patents #1,397 of 4,424Top 35%
GU Globalfoundries U.S.: 1 patents #344 of 665Top 55%
Overall (All Time): #408,938 of 4,157,543Top 10%
12
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
11239087 Fully depleted devices with slots in active regions Heng Yang, David Pritchard, Anurag Mittal, Hongru Ren, Manjunatha Prabhu +3 more 2022-02-01
10691862 Layouts for connecting contacts with metal tabs or vias Neha Nayyar, Daniel James Dechene, David Pritchard 2020-06-23
10497576 Devices with slotted active regions Heng Yang, David Pritchard, Anurag Mittal, Hongru Ren, Manjunatha Prabhu +3 more 2019-12-03
8716828 Semiconductor device with isolation trench liner Richard J. Carter, Michael Hargrove 2014-05-06
8217472 Semiconductor device with isolation trench liner Richard J. Carter, Michael Hargrove 2012-07-10
7998832 Semiconductor device with isolation trench liner, and related fabrication methods Richard J. Carter, Michael Hargrove 2011-08-16
7902599 Integrated circuit having long and short channel metal gate devices and method of manufacture Richard J. Carter, Michael Hargrove, John G. Pellerin 2011-03-08
7723192 Integrated circuit long and short channel metal gate devices and method of manufacture Richard J. Carter, Michael Hargrove, John G. Pellerin 2010-05-25
6458656 Process for creating a flash memory cell using a photoresist flow operation Stephen Keetai Park, Bharath Rangarajan 2002-10-01
6376308 Process for fabricating an EEPROM device having a pocket substrate region Fei Wang, David K. Foote, Bharath Rangarajan 2002-04-23
6362052 Use of an etch to reduce the thickness and around the edges of a resist mask during the creation of a memory cell Bharath Rangarajan, Fei Wang, Ursula Q. Quinto 2002-03-26
6168993 Process for fabricating a semiconductor device having a graded junction David K. Foote, Bharath Rangarajan, Fei Wang 2001-01-02