George J. Kluth — 12 Patents at AMD

George J. Kluth has been granted 12 US patents while listed as an inventor at AMD. The first was granted in 2001 and the most recent in February 2022. George J. Kluth ranks #396,045 of 4,157,543 US inventors in our database (top 9.5%). Patent records list George J. Kluth in Saratoga Springs, NY, US.

Issued Patents All Time

Showing 1–12 of 12 patents

Patent #	Title	Co-Inventors	Date	Approx Value ⓘ
11239087	Fully depleted devices with slots in active regions	Heng Yang, David Pritchard, Anurag Mittal, Hongru Ren, Manjunatha Prabhu +3 more	2022-02-01	$68,655,000
10691862	Layouts for connecting contacts with metal tabs or vias	Neha Nayyar, Daniel James Dechene, David Pritchard	2020-06-23	$59,393,000
10497576	Devices with slotted active regions	Heng Yang, David Pritchard, Anurag Mittal, Hongru Ren, Manjunatha Prabhu +3 more	2019-12-03	$65,885,000
8716828	Semiconductor device with isolation trench liner	Richard J. Carter, Michael Hargrove	2014-05-06	$1,570,000
8217472	Semiconductor device with isolation trench liner	Richard J. Carter, Michael Hargrove	2012-07-10	$3,144,000
7998832	Semiconductor device with isolation trench liner, and related fabrication methods	Richard J. Carter, Michael Hargrove	2011-08-16	$3,370,000
7902599	Integrated circuit having long and short channel metal gate devices and method of manufacture	Richard J. Carter, Michael Hargrove, John G. Pellerin	2011-03-08	$12,082,000
7723192	Integrated circuit long and short channel metal gate devices and method of manufacture	Richard J. Carter, Michael Hargrove, John G. Pellerin	2010-05-25	$6,565,000
6458656	Process for creating a flash memory cell using a photoresist flow operation	Stephen Keetai Park, Bharath Rangarajan	2002-10-01	$734,000
6376308	Process for fabricating an EEPROM device having a pocket substrate region	Fei Wang, David K. Foote, Bharath Rangarajan	2002-04-23	$2,653,000
6362052	Use of an etch to reduce the thickness and around the edges of a resist mask during the creation of a memory cell	Bharath Rangarajan, Fei Wang, Ursula Q. Quinto	2002-03-26	$3,803,000
6168993	Process for fabricating a semiconductor device having a graded junction	David K. Foote, Bharath Rangarajan, Fei Wang	2001-01-02	$6,157,000

George J. Kluth — 12 Patents

Issued Patents All Time

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