Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7591902 | Recirculation and reuse of dummy dispensed resist | Bharath Rangarajan, Ramkumar Subramanian, Khoi A. Phan, Michael Templeton | 2009-09-22 |
| 7153364 | Re-circulation and reuse of dummy-dispensed resist | Bharath Rangarajan, Ramkumar Subramanian, Khoi A. Phan, Michael K. Templeton | 2006-12-26 |
| 6612319 | Low defect EBR nozzle | Bharath Rangarajan, Khoi A. Phan | 2003-09-02 |
| 6593210 | Self-aligned/maskless reverse etch process using an inorganic film | Bharath Rangarajan, Bhanwar Singh | 2003-07-15 |
| 6562723 | Hybrid stack method for patterning source/drain areas | Bharath Rangarajan, Jeffrey A. Shields | 2003-05-13 |
| 6534243 | Chemical feature doubling process | Michael K. Templeton, Ramkumar Subramanian, Bharath Rangarajan, Kathleen R. Early | 2003-03-18 |
| 6439963 | System and method for mitigating wafer surface disformation during chemical mechanical polishing (CMP) | Bharath Rangarajan, Bhanwar Singh | 2002-08-27 |
| 6362052 | Use of an etch to reduce the thickness and around the edges of a resist mask during the creation of a memory cell | Bharath Rangarajan, Fei Wang, George J. Kluth | 2002-03-26 |
| 6277544 | Reverse lithographic process for semiconductor spaces | Bhanwar Singh, Bharath Rangarajan | 2001-08-21 |
| 6274289 | Chemical resist thickness reduction process | Ramkumar Subramanian, Michael K. Templeton, Bharath Rangarajan | 2001-08-14 |
| 6221777 | Reverse lithographic process for semiconductor vias | Bhanwar Singh, Bharath Rangarajan | 2001-04-24 |
| 6210846 | Exposure during rework for enhanced resist removal | Bharath Rangarajan, Bhanwar Singh | 2001-04-03 |