| 7590309 |
Image processing in integrated circuit technology development |
Paul J. Steffan |
2009-09-15 |
| 7263451 |
Method and apparatus for correlating semiconductor process data with known prior process data |
Shivananda Shetty, Paul J. Steffan |
2007-08-28 |
| 7208382 |
Semiconductor device with high conductivity region using shallow trench |
Kashmir Sahota, Emmanuil H. Lingunis, Nga-Ching Wong |
2007-04-24 |
| 7197435 |
Method and apparatus for using clustering method to analyze semiconductor devices |
Shivananda Shetty |
2007-03-27 |
| 7143370 |
Parameter linking system for data visualization in integrated circuit technology development |
— |
2006-11-28 |
| 7137085 |
Wafer level global bitmap characterization in integrated circuit technology development |
John Jianshi Wang, Siu May Ho, Srikanth Sundararajan, David C. Newbury, Shivananda Shetty +2 more |
2006-11-14 |
| 7101722 |
In-line voltage contrast determination of tunnel oxide weakness in integrated circuit technology development |
John Jianshi Wang, Wiley Eugene Hill |
2006-09-05 |
| 7099789 |
Characterizing distribution signatures in integrated circuit technology |
Franklyn Shihyu Wu, Paul J. Steffan, Jerry Tsiang, Shivananda Shetty, John Jianshi Wang |
2006-08-29 |
| 6875560 |
Testing multiple levels in integrated circuit technology development |
Paul J. Steffan, Shivananda Shetty |
2005-04-05 |
| 6864107 |
Determination of nonphotolithographic wafer process-splits in integrated circuit technology development |
Shivananda Shetty |
2005-03-08 |
| 6815233 |
Method of simultaneous display of die and wafer characterization in integrated circuit technology development |
Shivananda Shetty |
2004-11-09 |
| 6770523 |
Method for semiconductor wafer planarization by CMP stop layer formation |
Kashmir Sahota, Arvind Halliyal, Minh Van Ngo, Krishnashree Achuthan |
2004-08-03 |
| 6766265 |
Processing tester information by trellising in integrated circuit technology development |
Shivananda Shetty |
2004-07-20 |
| 6759179 |
Methods and systems for controlling resist residue defects at gate layer in a semiconductor device manufacturing process |
Khoi A. Phan, Jerry Cheng, Richard Bartlett, Anthony P. Coniglio, Wolfram Grundke +3 more |
2004-07-06 |
| 6723605 |
Method for manufacturing memory with high conductivity bitline and shallow trench isolation integration |
Kashmir Sahota |
2004-04-20 |
| 6649525 |
Methods and systems for controlling resist residue defects at gate layer in a semiconductor device manufacturing process |
Khoi A. Phan, Jerry Cheng, Richard Bartlett, Anthony P. Coniglio, Wolfram Grundke +3 more |
2003-11-18 |
| 6350696 |
Spacer etch method for semiconductor device |
Jeffrey A. Shields |
2002-02-26 |