Issued Patents All Time
Showing 1–2 of 2 patents
| Patent # | Title | Co-Inventors | Date | Approx Value ⓘ |
|---|---|---|---|---|
| 7135879 | Test structure and method for failure analysis of small contacts in integrated circuit technology development | Paul J. Steffan | 2006-11-14 | $38,989,000 |
| 7137085 | Wafer level global bitmap characterization in integrated circuit technology development | John Jianshi Wang, Siu May Ho, Jeffrey P. Erhardt, Srikanth Sundararajan, Shivananda Shetty +2 more | 2006-11-14 | $38,989,000 |