Issued Patents All Time
Showing 25 most recent of 69 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7590309 | Image processing in integrated circuit technology development | Jeffrey P. Erhardt | 2009-09-15 |
| 7263451 | Method and apparatus for correlating semiconductor process data with known prior process data | Jeffrey P. Erhardt, Shivananda Shetty | 2007-08-28 |
| 7251793 | Predicting defect future effects in integrated circuit technology development to facilitate semiconductor wafer lot disposition | — | 2007-07-31 |
| 7135879 | Test structure and method for failure analysis of small contacts in integrated circuit technology development | David C. Newbury | 2006-11-14 |
| 7137085 | Wafer level global bitmap characterization in integrated circuit technology development | John Jianshi Wang, Siu May Ho, Jeffrey P. Erhardt, Srikanth Sundararajan, David C. Newbury +2 more | 2006-11-14 |
| 7099789 | Characterizing distribution signatures in integrated circuit technology | Franklyn Shihyu Wu, Jeffrey P. Erhardt, Jerry Tsiang, Shivananda Shetty, John Jianshi Wang | 2006-08-29 |
| 6875560 | Testing multiple levels in integrated circuit technology development | Jeffrey P. Erhardt, Shivananda Shetty | 2005-04-05 |
| 6596591 | Methods to form reduced dimension bit-line isolation in the manufacture of non-volatile memory devices | Allen S. Yu, Chau M. Ho | 2003-07-22 |
| 6524916 | Controlled gate length and gate profile semiconductor device and manufacturing method therefor | Thomas C. Scholer, Allen S. Yu | 2003-02-25 |
| 6512842 | Composition based association engine for image archival systems | Allen S. Yu | 2003-01-28 |
| 6506639 | Method of forming low resistance reduced channel length transistors | Allen S. Yu | 2003-01-14 |
| 6468815 | Overlay radius offset shift engine | Allen S. Yu | 2002-10-22 |
| 6463171 | Automatic defect resizing tool | Allen S. Yu | 2002-10-08 |
| 6448606 | Semiconductor with increased gate coupling coefficient | Allen S. Yu, Thomas C. Scholer | 2002-09-10 |
| 6433371 | Controlled gate length and gate profile semiconductor device | Thomas C. Scholer, Allen S. Yu | 2002-08-13 |
| 6430572 | Recipe management database system | Allen S. Yu | 2002-08-06 |
| 6424881 | Computer generated recipe selector utilizing defect file information | Allen S. Yu | 2002-07-23 |
| 6423557 | ADC based in-situ destructive analysis selection and methodology therefor | Allen S. Yu | 2002-07-23 |
| 6421574 | Automatic defect classification system based variable sampling plan | Allen S. Yu | 2002-07-16 |
| 6395567 | Process control using ideal die data in an optical comparator scanning system | Allen S. Yu | 2002-05-28 |
| 6377898 | Automatic defect classification comparator die selection system | Allen S. Yu | 2002-04-23 |
| 6350639 | Simplified graded LDD transistor using controlled polysilicon gate profile | Allen S. Yu, Patrick K. Cheung | 2002-02-26 |
| 6338001 | In line yield prediction using ADC determined kill ratios die health statistics and die stacking | Allen S. Yu | 2002-01-08 |
| 6303394 | Global cluster pre-classification methodology | Allen S. Yu | 2001-10-16 |
| 6291252 | Automatic method to eliminate first-wafer effect | Allen S. Yu | 2001-09-18 |