Issued Patents All Time
Showing 25 most recent of 46 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11978591 | Mesoporous nanocrystalline film architecture for capacitive storage devices | Bruce S. Dunn, Sarah H. Tolbert, Torsten Brezesinski, George Gruner | 2024-05-07 |
| 10741337 | Mesoporous nanocrystalline film architecture for capacitive storage devices | Bruce S. Dunn, Sarah H. Tolbert, Torsten Brezesinski, George Gruner | 2020-08-11 |
| 10056199 | Mesoporous nanocrystalline film architecture for capacitive storage devices | Bruce S. Dunn, Sarah H. Tolbert, Torsten Brezesinski, George Gruner | 2018-08-21 |
| 9653219 | Mesoporous nanocrystalline film architecture for capacitive storage devices | Bruce S. Dunn, Sarah H. Tolbert, Torsten Brezesinski, George Gruner | 2017-05-16 |
| 8675346 | Mesoporous nanocrystalline film architecture for capacitive storage devices | Bruce S. Dunn, Sarah H. Tolbert, Torsten Brezesinski | 2014-03-18 |
| 7137085 | Wafer level global bitmap characterization in integrated circuit technology development | Siu May Ho, Jeffrey P. Erhardt, Srikanth Sundararajan, David C. Newbury, Shivananda Shetty +2 more | 2006-11-14 |
| 7101722 | In-line voltage contrast determination of tunnel oxide weakness in integrated circuit technology development | Jeffrey P. Erhardt, Wiley Eugene Hill | 2006-09-05 |
| 7099789 | Characterizing distribution signatures in integrated circuit technology | Franklyn Shihyu Wu, Jeffrey P. Erhardt, Paul J. Steffan, Jerry Tsiang, Shivananda Shetty | 2006-08-29 |
| 7020022 | Method of reference cell design for optimized memory circuit yield | Zhigang Wang, Xin Guo | 2006-03-28 |
| 6924220 | Self-aligned gate formation using polysilicon polish with peripheral protective layer | Kai Yang, Unsoon Kim | 2005-08-02 |
| 6825083 | Method for reducing shallow trench isolation edge thinning on thin gate oxides to improve peripheral transistor reliability and performance for high performance flash memory devices | Nian Yang, Xin Guo, Tien-Chun Yang | 2004-11-30 |
| 6797650 | Flash memory devices with oxynitride dielectric as the charge storage media | Zhigang Wang, Nian Yang, Jiang Li | 2004-09-28 |
| 6784061 | Process to improve the Vss line formation for high density flash memory and related structure associated therewith | Nian Yang, Hyeon-Seag Kim | 2004-08-31 |
| 6777957 | Test structure to measure interlayer dielectric effects and breakdown and detect metal defects in flash memories | Nian Yang, Zhigang Wang | 2004-08-17 |
| 6764920 | Method for reducing shallow trench isolation edge thinning on tunnel oxides using partial nitride strip and small bird's beak formation for high performance flash memory devices | Nian Yang, Unsoon Kim | 2004-07-20 |
| 6734080 | Semiconductor isolation material deposition system and method | Nian Yang, Tien-Chun Yang | 2004-05-11 |
| 6717850 | Efficient method to detect process induced defects in the gate stack of flash memory devices | Jiang Li, Nian Yang, Zhigang Wang | 2004-04-06 |
| 6590260 | Memory device having improved programmability | Nian Yang, Zhigang Wang | 2003-07-08 |
| 6445051 | Method and system for providing contacts with greater tolerance for misalignment in a flash memory | Mark S. Chang, Hao Fang, King Wai Kelwin Ko, Michael K. Templeton, Lu You +1 more | 2002-09-03 |
| 6423612 | Method of fabricating a shallow trench isolation structure with reduced topography | Wenge Yang, Fei Wang | 2002-07-23 |
| 6420240 | Method for reducing the step height of shallow trench isolation structures | Wenge Yang, Hao Fang | 2002-07-16 |
| 6410949 | Flash memory device with monitor structure for monitoring second gate over-etch | Kent Kuohua Chang, Hao Fang | 2002-06-25 |
| 6410458 | Method and system for eliminating voids in a semiconductor device | Lu You, Dawn Hopper | 2002-06-25 |
| 6380029 | Method of forming ono stacked films and DCS tungsten silicide gate to improve polycide gate performance for flash memory devices | Kent Kuohua Chang, Kenneth Wo-Wai Au | 2002-04-30 |
| 6376309 | Method for reduced gate aspect ratio to improve gap-fill after spacer etch | Kent Kuohua Chang, Hao Fang, Lu You | 2002-04-23 |