JW

John Jianshi Wang

AM AMD: 41 patents #198 of 9,279Top 3%
University of California: 5 patents #1,636 of 18,278Top 9%
Fujitsu Limited: 3 patents #8,614 of 24,456Top 40%
FL Fujitsu Amd Semiconductor Limited: 2 patents #3 of 40Top 8%
FL Fujitsu Semiconductor Limited: 1 patents #612 of 1,301Top 50%
📍 Glendora, CA: #5 of 353 inventorsTop 2%
🗺 California: #9,121 of 386,348 inventorsTop 3%
Overall (All Time): #62,564 of 4,157,543Top 2%
46
Patents All Time

Issued Patents All Time

Showing 26–46 of 46 patents

Patent #TitleCo-InventorsDate
6365945 Submicron semiconductor device having a self-aligned channel stop region and a method for fabricating the semiconductor device using a trim and etch Michael K. Templeton, Masaaki Higashitani 2002-04-02
6362049 High yield performance semiconductor process flow for NAND flash memory products Salvatore F. Cagnina, Hao Fang, Kent Kuohua Chang, Masaatzi Higashitani 2002-03-26
6355522 Effect of doped amorphous Si thickness on better poly 1 contact resistance performance for nand type flash memory devices Kent Kuohua Chang, Yuesong He 2002-03-12
6350627 Interlevel dielectric thickness monitor for complex semiconductor chips Tho Le La, Hao Fang 2002-02-26
6331954 Determination of misalignment for floating gates near a gate stack bending point in array of flash memory cells Jiang Li, Yider Wu 2001-12-18
6323047 Method for monitoring second gate over-etch in a semiconductor device Kent Kuohua Chang, Hao Fang 2001-11-27
6312991 Elimination of poly cap easy poly 1 contact for NAND product Hao Fang, Masaaki Higashitani 2001-11-06
6300658 Method for reduced gate aspect ration to improve gap-fill after spacer etch Kent Kuohua Chang, Hao Fang, Lu You 2001-10-09
6281078 Manufacturing process to eliminate ONO fence material in high density NAND-type flash memory devices Kent Kuohua Chang, Yuesong He, Ken D. Au 2001-08-28
6211058 Semiconductor device with multiple contact sizes Hao Fang 2001-04-03
6180454 Method for forming flash memory devices Kent Kuohua Chang, Wei-Wen Ou 2001-01-30
6177312 Method for removing contaminate nitrogen from the peripheral gate region of a non-volatile memory device during production of such device Yuesong He, Toru Ishigaki, Kent Kuohua Chang, Effiong Ibok 2001-01-23
6177316 Post barrier metal contact implantation to minimize out diffusion for NAND device Yue-Song He, Kent Kuohua Chang 2001-01-23
6140246 In-situ P doped amorphous silicon by NH3 to form oxidation resistant and finer grain floating gates Kent Kuohua Chang, Ken D. Au 2000-10-31
6072191 Interlevel dielectric thickness monitor for complex semiconductor chips Tho Le La, Hao Fang 2000-06-06
6066873 Method and apparatus for preventing P1 punchthrough Yuesong He, Kent Kuohua Chang 2000-05-23
6063668 Poly I spacer manufacturing process to eliminate polystringers in high density nand-type flash memory devices Yuesong He, Kent Kuohua Chang 2000-05-16
6057193 Elimination of poly cap for easy poly1 contact for NAND product Hao Fang, Masaaki Higashitani 2000-05-02
6017786 Method for forming a low barrier height oxide layer on a silicon substrate Yuesong He, Dae Yeong Joh 2000-01-25
5994780 Semiconductor device with multiple contact sizes Hao Fang 1999-11-30
5972749 Method for preventing P1 punchthrough Yuesong He, Kent Kuohua Chang 1999-10-26