Issued Patents All Time
Showing 25 most recent of 61 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8045314 | Method of atmospheric discharge energy conversion, storage and distribution | — | 2011-10-25 |
| 6800568 | Methods for the deposition of high-K films and high-K films produced thereby | — | 2004-10-05 |
| 6762454 | Stacked polysilicon layer for boron penetration inhibition | Joong S. Jeon, Arvind Halliyal, Minh Van Ngo | 2004-07-13 |
| 6735123 | High density dual bit flash memory cell with non planar structure | Nicholas H. Tripsas, Mark T. Ramsbey, Wei Zheng, Fred Cheung | 2004-05-11 |
| 6693004 | Interfacial barrier layer in semiconductor devices with high-K gate dielectric material | Arvind Halliyal, Joong S. Jeon, Minh Van Ngo, William G. En | 2004-02-17 |
| 6630383 | Bi-layer floating gate for improved work function between floating gate and a high-K dielectric layer | Wei Zheng, Nicholas H. Tripsas, Mark T. Ramsbey, Fred Cheung | 2003-10-07 |
| 6599810 | Shallow trench isolation formation with ion implantation | Nick Kepler, Olov Karlsson, Larry Wang, Basab Bandyopadhyay, Christopher F. Lyons | 2003-07-29 |
| 6593637 | Method for establishing component isolation regions in SOI semiconductor device | — | 2003-07-15 |
| 6472283 | MOS transistor processing utilizing UV-nitride removable spacer and HF etch | Emi Ishida, Srinath Krishman, Ming-Yin Hao | 2002-10-29 |
| 6472233 | MOSFET test structure for capacitance-voltage measurements | Khaled Ahmed, Nguyen Duc Bui, John R. Hauser | 2002-10-29 |
| 6451641 | Non-reducing process for deposition of polysilicon gate electrode over high-K gate dielectric material | Arvind Halliyal, Robert B. Ogle, Joong S. Jeon, Fred Cheung | 2002-09-17 |
| 6444555 | Method for establishing ultra-thin gate insulator using anneal in ammonia | — | 2002-09-03 |
| 6429083 | Removable spacer technology using ion implantation to augment etch rate differences of spacer materials | Emi Ishida, Srinath Krishnan, Ming-Yin Hao | 2002-08-06 |
| 6417041 | Method for fabricating high permitivity dielectric stacks having low buffer oxide | — | 2002-07-09 |
| 6399519 | Method for establishing ultra-thin gate insulator having annealed oxide and oxidized nitride | — | 2002-06-04 |
| 6391784 | Spacer-assisted ultranarrow shallow trench isolation formation | — | 2002-05-21 |
| 6380047 | Shallow trench isolation formation with two source/drain masks and simplified planarization mask | Basab Bandyopadhyay, Nick Kepler, Olov Karlsson, Larry Wang, Christopher F. Lyons | 2002-04-30 |
| 6372582 | Indium retrograde channel doping for improved gate oxide reliability | Richard P. Rouse, Ming-Yin Hao, Emi Ishida | 2002-04-16 |
| 6344396 | Removable spacer technology using ion implantation for forming asymmetric MOS transistors | Emi Ishida, Srinath Krishman, Ming-Yin Hao | 2002-02-05 |
| 6342423 | MOS-type transistor processing utilizing UV-nitride removable spacer and HF etch | Emi Ishida, Srinath Krishnan, Ming-Yin Hao | 2002-01-29 |
| 6329256 | Self-aligned damascene gate formation with low gate resistance | — | 2001-12-11 |
| 6319857 | Method of fabricating stacked N-O-N ultrathin gate dielectric structures | — | 2001-11-20 |
| 6239031 | Stepper alignment mark structure for maintaining alignment integrity | Nick Kepler, Olov Karlsson, Larry Wang, Basab Bandyopadhyah, Christopher F. Lyons | 2001-05-29 |
| 6235607 | Method for establishing component isolation regions in SOI semiconductor device | — | 2001-05-22 |
| 6235456 | Graded anti-reflective barrier films for ultra-fine lithography | — | 2001-05-22 |