| 12293184 |
Illegal address mask method and device for cores of DSP |
Haibin Zhou, Guoqiang He, Wenjun HAN |
2025-05-06 |
|
| D1044541 |
Wristband |
— |
2024-10-01 |
|
| 6894364 |
Capacitor in an interconnect system and method of manufacturing thereof |
Tri-Rung Yew, Coming Chen, Tsong-Minn Hsieh, Nai-Chen Peng, Jih-Cheng Yeh |
2005-05-17 |
$1,090,000 |
| 6506640 |
Multiple channel implantation to form retrograde channel profile and to engineer threshold voltage and sub-surface punch-through |
Emi Ishida, Deepak Nayak |
2003-01-14 |
$2,234,000 |
| 6475868 |
Oxygen implantation for reduction of junction capacitance in MOS transistors |
Asim A. Selcuk, Richard P. Rouse, Emi Ishida |
2002-11-05 |
$1,578,000 |
| 6472283 |
MOS transistor processing utilizing UV-nitride removable spacer and HF etch |
Emi Ishida, Srinath Krishman, Effiong Ibok |
2002-10-29 |
$1,498,000 |
| 6444550 |
Laser tailoring retrograde channel profile in surfaces |
Emi Ishida |
2002-09-03 |
$1,843,000 |
| 6429083 |
Removable spacer technology using ion implantation to augment etch rate differences of spacer materials |
Emi Ishida, Srinath Krishnan, Effiong Ibok |
2002-08-06 |
$1,934,000 |
| 6423601 |
Retrograde well structure formation by nitrogen implantation |
Emi Ishida |
2002-07-23 |
$1,368,000 |
| 6410393 |
Semiconductor device with asymmetric channel dopant profile |
Emi Ishida |
2002-06-25 |
$2,000,000 |
| 6372590 |
Method for making transistor having reduced series resistance |
Deepak Nayak |
2002-04-16 |
$2,231,000 |
| 6372582 |
Indium retrograde channel doping for improved gate oxide reliability |
Richard P. Rouse, Emi Ishida, Effiong Ibok |
2002-04-16 |
$2,231,000 |
| 6344396 |
Removable spacer technology using ion implantation for forming asymmetric MOS transistors |
Emi Ishida, Srinath Krishman, Effiong Ibok |
2002-02-05 |
$5,814,000 |
| 6342423 |
MOS-type transistor processing utilizing UV-nitride removable spacer and HF etch |
Emi Ishida, Srinath Krishnan, Effiong Ibok |
2002-01-29 |
$11,164,000 |
| 6316303 |
Method of fabricating a MOS transistor having SEG silicon |
Tony Lin, Chien-Chao Huang |
2001-11-13 |
$597,000 |
| 6316322 |
Method for fabricating semiconductor device |
— |
2001-11-13 |
$7,839,000 |
| 6306702 |
Dual spacer method of forming CMOS transistors with substantially the same sub 0.25 micron gate length |
Richard P. Rouse, Zicheng Gary Ling |
2001-10-23 |
$2,669,000 |
| 6297112 |
Method of forming a MOS transistor |
Tony Lin, Tung-Po Chen |
2001-10-02 |
$470,000 |
| 6274915 |
Method of improving MOS device performance by controlling degree of depletion in the gate electrode |
Srinath Krishnan, David Bang, Witold P. Maszara |
2001-08-14 |
$3,163,000 |
| 6245689 |
Process for reliable ultrathin oxynitride formation |
Robert B. Ogle, Derick J. Wristers |
2001-06-12 |
$5,669,000 |
| 6194259 |
Forming retrograde channel profile and shallow LLDD/S-D extensions using nitrogen implants |
Deepak Nayak |
2001-02-27 |
$7,317,000 |
| 6187687 |
Minimization of line width variation in photolithography |
Marina V. Plat |
2001-02-13 |
$5,609,000 |
| 6051460 |
Preventing boron penetration through thin gate oxide of P-channel devices by doping polygate with silicon |
Deepak Nayak |
2000-04-18 |
$8,077,000 |
| 5973370 |
Preventing boron penetration through thin gate oxide of P-channel devices in advanced CMOS technology |
Deepak Nayak |
1999-10-26 |
$1,975,000 |
| 5939763 |
Ultrathin oxynitride structure and process for VLSI applications |
Robert B. Ogle, Derick J. Wristers |
1999-08-17 |
$2,185,000 |
