Issued Patents All Time
Showing 1–25 of 61 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11380762 | Semiconductor device having semiconductor alloy layer adjacent a gate structure | Yee-Chia Yeo, Chao-Hsiung Wang, Chun-Chieh Lin, Chenming Hu | 2022-07-05 |
| 10818754 | Semiconductor device with silicided source/drain region | Yee-Chia Yeo, Chao-Hsiung Wang, Chun-Chieh Lin, Chenming Hu | 2020-10-27 |
| 10446646 | Cobalt silicidation process for substrates comprised with a silicon-germanium layer | Yee-Chia Yeo, Chao-Hsiung Wang, Chun-Chieh Lin, Chenming Hu | 2019-10-15 |
| 9905474 | CMOS device with raised source and drain regions | Chun-Sheng Liang, Hung-Ming Chen, Fu-Liang Yang | 2018-02-27 |
| 9673280 | Cobalt silicidation process for substrates comprised with a silicon-germanium layer | Yee-Chia Yeo, Chao-Hsiung Wang, Chun-Chieh Lin, Chenming Hu | 2017-06-06 |
| 8847253 | Programming optical device | Fu-Liang Yang | 2014-09-30 |
| 8835291 | Strained gate electrodes in semiconductor devices | Fu-Liang Yang | 2014-09-16 |
| 8792078 | Method and pellicle mounting apparatus for reducing pellicle induced distortion | Cheng-Ming Lin, Jong-Yuh Chang, Chia-Wei Chang, Boming Hsu | 2014-07-29 |
| 8679728 | Method for fabricating patterned layer | Chun-Chi Chen, Shyi-Long Shy, Cheng-San Wu, Fu-Liang Yang | 2014-03-25 |
| 8569845 | Strained silicon device | Cheng-Chuan Huang, Fu-Liang Yang | 2013-10-29 |
| 8564018 | Relaxed silicon germanium substrate with low defect density | Chun Chich Lin, Yee-Chia Yeo, Chao-Hsiung Wang, Tien-Chih Chang, Chenming Hu +4 more | 2013-10-22 |
| 8319962 | Mask making decision for manufacturing (DFM) on mask quality control | Chih-Chiang Tu | 2012-11-27 |
| 8311666 | System and method for separating defective dies from wafer | Te-Chun Chen, Cheng-Tao Tsai | 2012-11-13 |
| 8288842 | Method for dicing semiconductor wafers | Hsin-Hui Lee, Chao-Hsiung Wang, Fu-Liang Yang, Chenming Hu | 2012-10-16 |
| 8120767 | Mask making decision for manufacturing (DFM) on mask quality control | Chih-Chiang Tu | 2012-02-21 |
| 8008157 | CMOS device with raised source and drain regions | Chun-Sheng Liang, Hung-Ming Chen, Fu-Liang Yang | 2011-08-30 |
| 7923759 | Metal gate semiconductor device and manufacturing method | Kuang-Hsin Chen, Fu-Liang Yang | 2011-04-12 |
| 7871742 | Method for controlling phase angle of a mask by post-treatment | Chun-Lang Chen, Tran-Hui Shen, Fei-Gwo Tsai | 2011-01-18 |
| 7745904 | Shallow trench isolation structure for semiconductor device | Chih-Hsin Ko, Chung-Hu Ke | 2010-06-29 |
| 7638376 | Method for forming SOI device | Cheng-Kuo Wen, Hao Chen, Fu-Liang Yang, Hsun-Chih Tsao | 2009-12-29 |
| 7602006 | Semiconductor flash device | Chi Min-Hwa, Fu-Liang Yang | 2009-10-13 |
| 7582947 | High performance device design | Fu-Liang Yang | 2009-09-01 |
| 7571421 | System, method, and computer-readable medium for performing data preparation for a mask design | Peng Chen, Chih-Chiang Tu | 2009-08-04 |
| 7547605 | Microelectronic device and a method for its manufacture | — | 2009-06-16 |
| 7545006 | CMOS devices with graded silicide regions | Hung-Ming Chen, Fu-Liang Yang | 2009-06-09 |