Issued Patents All Time
Showing 1–25 of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9673105 | CMOS devices with Schottky source and drain regions | Chih-Hsin Ko, Hung-Wei Chen, Wen-Chin Lee | 2017-06-06 |
| 8569837 | MOS devices having elevated source/drain regions | Chih-Hsin Ko, Hung-Wei Chen, Ta-Ming Kuan, Wen-Chin Lee | 2013-10-29 |
| 8426298 | CMOS devices with Schottky source and drain regions | Chih-Hsin Ko, Hung-Wei Chen, Wen-Chin Lee | 2013-04-23 |
| 8154107 | Semiconductor device and a method of fabricating the device | Chih-Hsin Ko, Wen-Chin Lee | 2012-04-10 |
| 8084305 | Isolation spacer for thin SOI devices | Chih-Hsin Ko, Wen-Chin Lee, Yee-Chia Yeo | 2011-12-27 |
| 8039284 | Dual metal silicides for lowering contact resistance | Chih-Hsin Ko, Hung-Wei Chen, Wen-Chin Lee | 2011-10-18 |
| 8030210 | Contact barrier structure and manufacturing methods | Ching-Ya Wang, Wen-Chin Lee | 2011-10-04 |
| 7985652 | Metal stress memorization technology | Ta-Ming Kuan, Chih-Hsin Ko, Wen-Chin Lee | 2011-07-26 |
| 7875959 | Semiconductor structure having selective silicide-induced stress and a method of producing same | Wen-Chin Lee, Chenming Hu | 2011-01-25 |
| 7803718 | BiCMOS performance enhancement by mechanical uniaxial strain and methods of manufacture | Chih-Hsin Ko, Tzu-Juei Wang, Hung-Wei Chen, Wen-Chin Lee | 2010-09-28 |
| 7745904 | Shallow trench isolation structure for semiconductor device | Chih-Hsin Ko, Chien-Chao Huang | 2010-06-29 |
| 7737532 | Hybrid Schottky source-drain CMOS for high mobility and low barrier | Chih-Hsin Ko, Hung-Wei Chen, Wen-Chin Lee, Min-hwa Chi | 2010-06-15 |
| 7709903 | Contact barrier structure and manufacturing methods | Ching-Ya Wang, Wen-Chin Lee | 2010-05-04 |
| 7582934 | Isolation spacer for thin SOI devices | Chih-Hsin Ko, Wen-Chin Lee, Yee-Chia Yeo | 2009-09-01 |
| 7569896 | Transistors with stressed channels | Chih-Hsin Ko, Hung-Wei Chen, Wen-Chin Lee | 2009-08-04 |
| 7538398 | System and method for forming a semiconductor device source/drain contact | Ching-Ya Wang, Wen-Chin Lee | 2009-05-26 |
| 7511348 | MOS transistors with selectively strained channels | Chih-Hsin Ko, Wen-Chin Lee, Hung-Wei Chen | 2009-03-31 |
| 7465620 | Transistor mobility improvement by adjusting stress in shallow trench isolation | Chih-Hsin Ko, Chien-Chao Huang | 2008-12-16 |
| 7466008 | BiCMOS performance enhancement by mechanical uniaxial strain and methods of manufacture | Chih-Hsin Ko, Tzu-Juei Wang, Hung-Wei Chen, Wen-Chin Lee | 2008-12-16 |
| 7394136 | High performance semiconductor devices fabricated with strain-induced processes and methods for making same | Wen-Chin Lee, Yee-Chia Yeo, Chih-Hsin Ko, Chenming Hu | 2008-07-01 |
| 7358571 | Isolation spacer for thin SOI devices | Chih-Hsin Ko, Wen-Chin Lee, Yee-Chia Yeo | 2008-04-15 |
| 7355262 | Diffusion topography engineering for high performance CMOS fabrication | Chih-Hsin Ko, Wen-Chin Lee, Hung-Wei Chen | 2008-04-08 |
| 7238564 | Method of forming a shallow trench isolation structure | Chih-Hsin Ko, Chien-Chao Huang | 2007-07-03 |
| 7190036 | Transistor mobility improvement by adjusting stress in shallow trench isolation | Chih-Hsin Ko, Chien-Chao Huang | 2007-03-13 |
| 7176537 | High performance CMOS with metal-gate and Schottky source/drain | Wen-Chin Lee, Min-hwa Chi | 2007-02-13 |