Issued Patents All Time
Showing 1–25 of 131 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12040379 | 3D capacitor and method of manufacturing same | Chi-Wen Liu | 2024-07-16 |
| 12027522 | Systems and methods for fabricating FinFETs with different threshold voltages | Chi-Wen Liu | 2024-07-02 |
| 11894448 | Structure and method for vertical tunneling field effect transistor with leveled source and drain | Harry-Hak-Lay Chuang, Yi-Ren Chen, Chi-Wen Liu, Ming Zhu | 2024-02-06 |
| 11837646 | 3D capacitor and method of manufacturing same | Chi-Wen Liu | 2023-12-05 |
| 11735618 | Stacked grid design for improved optical performance and isolation | Yun-Wei Cheng, Horng-Huei Tseng, Chun-Hao Chou, Tsung-Han Tsai, Kuo-Cheng Lee +2 more | 2023-08-22 |
| 11380762 | Semiconductor device having semiconductor alloy layer adjacent a gate structure | Chien-Chao Huang, Yee-Chia Yeo, Chun-Chieh Lin, Chenming Hu | 2022-07-05 |
| 11362087 | Systems and methods for fabricating FinFETs with different threshold voltages | Chi-Wen Liu | 2022-06-14 |
| 11205594 | Fin spacer protected source and drain regions in FinFETs | Kuo-Cheng Chiang, Ting-Hung Hsu, Chi-Wen Liu | 2021-12-21 |
| 11133301 | Integrated circuit having a MOM capacitor and transistor | Chi-Wen Liu | 2021-09-28 |
| 11121168 | Stacked grid design for improved optical performance and isolation | Yun-Wei Cheng, Horng-Huei Tseng, Chun-Hao Chou, Tsung-Han Tsai, Kuo-Cheng Lee +2 more | 2021-09-14 |
| 11101371 | Structure and method for vertical tunneling field effect transistor with leveled source and drain | Harry-Hak-Lay Chuang, Yi-Ren Chen, Chi-Wen Liu, Ming Zhu | 2021-08-24 |
| 11075278 | 3D capacitor based on fin structure having low-resistance surface and method of manufacturing same | Chi-Wen Liu | 2021-07-27 |
| 11004886 | Stacked grid design for improved optical performance and isolation | Yun-Wei Cheng, Horng-Huei Tseng, Chun-Hao Chou, Tsung-Han Tsai, Kuo-Cheng Lee +2 more | 2021-05-11 |
| 10998425 | FinFET structure and method for fabricating the same | Kuo-Cheng Chiang, Guan-Lin Chen, Chi-Wen Liu | 2021-05-04 |
| 10978461 | Antifuse array and method of forming antifuse using anodic oxidation | Jenn-Gwo Hwu, Wei-Cheng Tian, Samuel C. Pan, Chi-Wen Liu | 2021-04-13 |
| 10847389 | Systems and methods for annealing semiconductor structures | Chun Hsiung Tsai, Zi-Wei Fang | 2020-11-24 |
| 10818754 | Semiconductor device with silicided source/drain region | Chien-Chao Huang, Yee-Chia Yeo, Chun-Chieh Lin, Chenming Hu | 2020-10-27 |
| 10679900 | Fin spacer protected source and drain regions in FinFETs | Kuo-Cheng Chiang, Ting-Hung Hsu, Chi-Wen Liu | 2020-06-09 |
| 10679990 | Multi-fin device and method of making same | Chi-Wen Liu | 2020-06-09 |
| 10622480 | Forming gate stacks of FinFETs through oxidation | Kuo-Cheng Chiang, Jiun-Jia Huang, Chi-Wen Liu | 2020-04-14 |
| 10504907 | Antifuse array and method of forming antifuse using anodic oxidation | Jenn-Gwo Hwu, Wei-Cheng Tian, Samuel C. Pan, Chi-Wen Liu | 2019-12-10 |
| 10453716 | Systems and methods for annealing semiconductor structures | Chun Hsiung Tsai, Zi-Wei Fang | 2019-10-22 |
| 10446646 | Cobalt silicidation process for substrates comprised with a silicon-germanium layer | Chien-Chao Huang, Yee-Chia Yeo, Chun-Chieh Lin, Chenming Hu | 2019-10-15 |
| 10340191 | Method of forming a fin structure of semiconductor device | Kuo-Cheng Ching, Jiun-Jia Huang, Chi-Wen Liu | 2019-07-02 |
| 10283613 | 3D capacitor and method of manufacturing same | Chi-Wen Liu | 2019-05-07 |