Issued Patents All Time
Showing 1–25 of 458 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12431214 | External magnetic field detection for MRAM device | Yuan-Jen Lee, Tien-Wei Chiang, Yi-Chun Shih | 2025-09-30 |
| 12426260 | Memory device with one-time programmable memory unit and method for fabricating the same | Wen-Chun You, Hung Cho Wang | 2025-09-23 |
| 12426333 | Polysilicon design for replacement gate technology | Kong-Beng Thei, Sheng-Chen Chung, Chiung-Han Yeh, Lee-Wee Teo, Yu-Ying Hsu +1 more | 2025-09-23 |
| 12426514 | Techniques for MRAM MTJ top electrode connection | Chen-Pin Hsu, Hung Cho Wang, Wen-Chun You, Sheng-Chang Chen, Tsun Chung Tu +2 more | 2025-09-23 |
| 12426274 | Method for MRAM top electrode connection | Hung Cho Wang, Sheng-Chang Chen, Sheng-Huang Huang | 2025-09-23 |
| 12414380 | Method for forming an integrated chip (IC) including forming a through substrate via (TSV) in an isolation structure formed in a first opening that formed in a metal substrate layer | Hsin Fu Lin, Chien-Hung Liu | 2025-09-09 |
| 12408439 | Integrated chip (IC) having conductive TSV extended through SOI substrate comprising a semiconductor device layer, an insulating layer and a metal layer | Hsin Fu Lin, Chien-Hung Liu | 2025-09-02 |
| 12400983 | Semiconductor packages and methods of manufacturing thereof | Wei-Cheng Wu, Wen-Tuo Huang, Yu-Ling Hsu, Pai Chi Chou, Ya-Chi Hung | 2025-08-26 |
| 12389672 | Method to embed planar FETs with finFETs | Wei-Cheng Wu, Li-Feng Teng, Li-Jung Liu | 2025-08-12 |
| 12374658 | Bonded wafer device structure and methods for making the same | Wei-Cheng Wu, Wen-Tuo Huang | 2025-07-29 |
| 12369327 | MFM device with an enhanced bottom electrode | Fu-Chen Chang, Tzu-Yu Chen, Sheng-Hung Shih, Kuo-Chi Tu | 2025-07-22 |
| 12354951 | Layout for reducing loading at line sockets and/or for increasing overlay tolerance while cutting lines | Kuo-Chyuan Tzeng, Wan-Chen Chen, Chang-Chih Huang | 2025-07-08 |
| 12342730 | Magnetic tunnel junction structures with protection outer layers | Sheng-Chang Chen, Hung Cho Wang, Sheng-Huang Huang | 2025-06-24 |
| 12342610 | Method of manufacturing semiconductor device | Wei-Cheng Wu | 2025-06-24 |
| 12336229 | Split gate memory device and method of fabricating the same | Chang-Ming Wu, Wei-Cheng Wu, Shih-Chang Liu, Chia-Shiung Tsai | 2025-06-17 |
| 12329039 | Magnetic tunnel junction structures with protection outer layers | Sheng-Chang Chen, Hung Cho Wang, Sheng-Huang Huang | 2025-06-10 |
| 12324156 | Memory devices and method of fabricating same | Chang-Ming Wu, Wei-Cheng Wu, Shih-Chang Liu, Chia-Shiung Tsai | 2025-06-03 |
| 12322715 | Method of forming integrated chip structure having slotted bond pad in stacked wafer structure | Li-Feng Teng, Wei-Cheng Wu | 2025-06-03 |
| 12302628 | Integrated chip with solid-state power storage device | Yi Ching Ong, Kuen-Yi Chen, Yi-Hsuan Chen, Kuo-Ching Huang | 2025-05-13 |
| 12300566 | Integrated chip with good thermal dissipation performance | Hsin Fu Lin, Shiang-Hung Huang, Tsung-Hao Yeh | 2025-05-13 |
| 12284814 | Semiconductor structure and manufacturing method of the same | Sheng-Huang Huang, Keng-Ming Kuo, Hung Cho Wang | 2025-04-22 |
| 12279437 | MRAM memory cell layout for minimizing bitcell area | Wen-Chun You, Hung Cho Wang, Yen-Yu Shih | 2025-04-15 |
| 12274182 | Sidewall spacer structure for memory cell | Yao-Wen Chang, Chung-Chiang Min, Hung Cho Wang, Tsung-Hsueh Yang, Yuan-Tai Tseng +2 more | 2025-04-08 |
| 12274072 | Semiconductor memory device and method for fabricating the same | Sheng-Huang Huang, Shih-Chang Liu, Chern-Yow Hsu | 2025-04-08 |
| 12274183 | Memory cell with top electrode via | Ming-Che Ku, Hung Cho Wang, Tsun Chung Tu, Jiunyu Tsai, Sheng-Huang Huang | 2025-04-08 |