Issued Patents All Time
Showing 1–25 of 72 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12426260 | Memory device with one-time programmable memory unit and method for fabricating the same | Harry-Hak-Lay Chuang, Wen-Chun You | 2025-09-23 |
| 12426514 | Techniques for MRAM MTJ top electrode connection | Harry-Hak-Lay Chuang, Chen-Pin Hsu, Wen-Chun You, Sheng-Chang Chen, Tsun Chung Tu +2 more | 2025-09-23 |
| 12426274 | Method for MRAM top electrode connection | Harry-Hak-Lay Chuang, Sheng-Chang Chen, Sheng-Huang Huang | 2025-09-23 |
| 12342730 | Magnetic tunnel junction structures with protection outer layers | Sheng-Chang Chen, Harry-Hak-Lay Chuang, Sheng-Huang Huang | 2025-06-24 |
| 12329039 | Magnetic tunnel junction structures with protection outer layers | Sheng-Chang Chen, Harry-Hak-Lay Chuang, Sheng-Huang Huang | 2025-06-10 |
| 12317754 | Magnetic tunnel junction structures and related methods | Jun Chen, Chun-Heng Liao | 2025-05-27 |
| 12284814 | Semiconductor structure and manufacturing method of the same | Harry-Hak-Lay Chuang, Sheng-Huang Huang, Keng-Ming Kuo | 2025-04-22 |
| 12279437 | MRAM memory cell layout for minimizing bitcell area | Harry-Hak-Lay Chuang, Wen-Chun You, Yen-Yu Shih | 2025-04-15 |
| 12274182 | Sidewall spacer structure for memory cell | Yao-Wen Chang, Chung-Chiang Min, Harry-Hak-Lay Chuang, Tsung-Hsueh Yang, Yuan-Tai Tseng +2 more | 2025-04-08 |
| 12274183 | Memory cell with top electrode via | Ming-Che Ku, Harry-Hak-Lay Chuang, Tsun Chung Tu, Jiunyu Tsai, Sheng-Huang Huang | 2025-04-08 |
| 12256647 | Embedded MRAM fabrication process for ion beam etching with protection by top electrode spacer | Jun Chen, Harry-Hak-Lay Chuang | 2025-03-18 |
| 12250826 | Integrated circuit device and method for fabricating the same | Yuan-Jen Lee, Harry-Hak-Lay Chuang, Tien-Wei Chiang, Kuei-Hung Shen, Sheng-Huang Huang | 2025-03-11 |
| 12250888 | Method and structure for improved memory integrity at array boundaries | Jun Chen, Harry-Hak-Lay Chuang | 2025-03-11 |
| 12223989 | Semiconductor device and method for fabricating the same | Harry-Hak-Lay Chuang, Sheng-Huang Huang, Sheng-Chang Chen | 2025-02-11 |
| 12167614 | Techniques for MRAM MTJ top electrode to via interface | Harry-Hak-Lay Chuang, Jiunyu Tsai, Sheng-Huang Huang | 2024-12-10 |
| 12069963 | Magnetic random access memory device and formation method thereof | Harry-Hak-Lay Chuang, Sheng-Chang Chen, Sheng-Huang Huang | 2024-08-20 |
| 12027420 | Etch stop layer for memory device formation | Sheng-Huang Huang, Chung-Chiang Min, Harry-Hak-Lay Chuang, Sheng-Chang Chen | 2024-07-02 |
| 11910619 | Method for MRAM top electrode connection | Harry-Hak-Lay Chuang, Sheng-Chang Chen, Sheng-Huang Huang | 2024-02-20 |
| 11889769 | Memory cell with top electrode via | Ming-Che Ku, Harry-Hak-Lay Chuang, Tsun Chung Tu, Jiunyu Tsai, Sheng-Huang Huang | 2024-01-30 |
| 11856868 | Magnetic tunnel junction structures and related methods | Jun Chen, Chun-Heng Liao | 2023-12-26 |
| 11832529 | Memory device | Harry-Hak-Lay Chuang, Tong-Chern Ong, Wen-Ting Chu, Yu-Wen Liao, Kuei-Hung Shen +2 more | 2023-11-28 |
| 11818962 | Sidewall spacer structure for memory cell | Yao-Wen Chang, Chung-Chiang Min, Harry-Hak-Lay Chuang, Tsung-Hsueh Yang, Yuan-Tai Tseng +2 more | 2023-11-14 |
| 11800724 | MRAM memory cell layout for minimizing bitcell area | Harry-Hak-Lay Chuang, Wen-Chun You, Yen-Yu Shih | 2023-10-24 |
| 11785862 | Via landing enhancement for memory device | Chun-Heng Liao, Harry-Hak-Lay Chuang, Chang-Jen Hsieh | 2023-10-10 |
| 11723219 | Semiconductor structure and manufacturing method of the same | Harry-Hak-Lay Chuang, Sheng-Huang Huang, Keng-Ming Kuo | 2023-08-08 |