Issued Patents All Time
Showing 26–50 of 458 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12262643 | Techniques for MRAM MTJ top electrode connection | Chern-Yow Hsu, Shih-Chang Liu | 2025-03-25 |
| 12256647 | Embedded MRAM fabrication process for ion beam etching with protection by top electrode spacer | Jun Chen, Hung Cho Wang | 2025-03-18 |
| 12255133 | Electrical fuse (e-fuse) one-time programmable (OTP) device and manufacturing method thereof | Alexander Kalnitsky, Wei-Cheng Wu, Chia-Wen Liang, Li-Feng Teng | 2025-03-18 |
| 12250826 | Integrated circuit device and method for fabricating the same | Yuan-Jen Lee, Tien-Wei Chiang, Hung Cho Wang, Kuei-Hung Shen, Sheng-Huang Huang | 2025-03-11 |
| 12250888 | Method and structure for improved memory integrity at array boundaries | Jun Chen, Hung Cho Wang | 2025-03-11 |
| 12245437 | Semiconductor device | Wu-Chang Tsai, Tien-Wei Chiang | 2025-03-04 |
| 12223989 | Semiconductor device and method for fabricating the same | Sheng-Huang Huang, Hung Cho Wang, Sheng-Chang Chen | 2025-02-11 |
| 12217975 | Semiconductor device having metal gate and poly gate | Alexander Kalnitsky, Wei-Cheng Wu | 2025-02-04 |
| 12218074 | DC and AC magnetic field protection for MRAM device using magnetic-field-shielding structure | Tien-Wei Chiang, Kuo-An Liu, Chia-Hsiang Chen | 2025-02-04 |
| 12210055 | Semiconductor wafer testing system and related method for improving external magnetic field wafer testing | Chih-Yang Chang, Ching-Huang Wang, Tien-Wei Chiang, Meng-Chun Shih, Chia Yu Wang | 2025-01-28 |
| 12191262 | Package structure and method for fabricating the same | Chia-Hsiang Chen, Meng-Chun Shih, Ching-Huang Wang, Tien-Wei Chiang | 2025-01-07 |
| 12191282 | Shared pad/bridge layout for a 3D IC | Wei-Cheng Wu, Wen-Tuo Huang, Chia-Sheng Lin, Wei Chuang Wu, Shih Kuang Yang +5 more | 2025-01-07 |
| 12167614 | Techniques for MRAM MTJ top electrode to via interface | Hung Cho Wang, Jiunyu Tsai, Sheng-Huang Huang | 2024-12-10 |
| 12136627 | 3DIC structure for high voltage device on a SOI substrate | Wen-Tuo Huang, Hsin Fu Lin, Wei-Cheng Wu | 2024-11-05 |
| 12133470 | Semiconductor structure and method of forming the same | Kuei-Hung Shen, Chern-Yow Hsu, Shih-Chang Liu | 2024-10-29 |
| 12107001 | Semiconductor feature and method for manufacturing the same | Chung-Jen Huang, Wen-Tuo Huang, Wei-Cheng Wu | 2024-10-01 |
| 12068313 | Semiconductor arrangement and formation thereof | Wei-Cheng Wu, Shih-Chang Liu, Ming Chyi Liu | 2024-08-20 |
| 12069963 | Magnetic random access memory device and formation method thereof | Sheng-Chang Chen, Hung Cho Wang, Sheng-Huang Huang | 2024-08-20 |
| 12027420 | Etch stop layer for memory device formation | Sheng-Huang Huang, Chung-Chiang Min, Hung Cho Wang, Sheng-Chang Chen | 2024-07-02 |
| 12015029 | Method to embed planar FETs with finFETs | Wei-Cheng Wu, Li-Feng Teng, Li-Jung Liu | 2024-06-18 |
| 11978740 | Semiconductor-on-insulator (SOI) semiconductor structures including a high-k dielectric layer and methods of manufacturing the same | Kuo-Ching Huang, Wei-Cheng Wu, Hsin Fu Lin, Henry Wang, Chien-Hung Liu +2 more | 2024-05-07 |
| 11961826 | Bonded wafer device structure and methods for making the same | Wei-Cheng Wu, Wen-Tuo Huang | 2024-04-16 |
| 11935918 | High voltage device with boosted breakdown voltage | Hsin Fu Lin, Tsung-Hao Yeh | 2024-03-19 |
| 11930645 | Semiconductor structure integrated with magnetic tunneling junction | Alexander Kalnitsky, Sheng-Haung Huang, Tien-Wei Chiang | 2024-03-12 |
| 11910619 | Method for MRAM top electrode connection | Hung Cho Wang, Sheng-Chang Chen, Sheng-Huang Huang | 2024-02-20 |