Issued Patents All Time
Showing 1–25 of 42 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12191282 | Shared pad/bridge layout for a 3D IC | Harry-Hak-Lay Chuang, Wei-Cheng Wu, Wen-Tuo Huang, Chia-Sheng Lin, Wei Chuang Wu +5 more | 2025-01-07 |
| 12165955 | Semiconductor arrangement and method for making | Josh Lin, Yun-Chi Wu, Tsung-Yu Yang | 2024-12-10 |
| 12144173 | Seal method to integrate non-volatile memory (NVM) into logic or bipolar CMOS DMOS (BCD) technology | Cheng-Bo Shu, Yun-Chi Wu | 2024-11-12 |
| 12114503 | Integrated chip including a tunnel dielectric layer which has different thicknesses over a protrusion region of a substrate | Jui-Yu Pan, Cheng-Bo Shu, Jing-Ru Lin, Tsung-Yu Yang, Yun-Chi Wu +1 more | 2024-10-08 |
| 12107001 | Semiconductor feature and method for manufacturing the same | Harry-Hak-Lay Chuang, Wen-Tuo Huang, Wei-Cheng Wu | 2024-10-01 |
| 12094984 | Semiconductor device | Cheng-Bo Shu, Yun-Chi Wu | 2024-09-17 |
| 11854942 | Semiconductor arrangement and method for making | Josh Lin, Yun-Chi Wu, Tsung-Yu Yang | 2023-12-26 |
| 11764103 | Semiconductor feature and method for manufacturing the same | Harry-Hak-Lay Chuang, Wen-Tuo Huang, Wei-Cheng Wu | 2023-09-19 |
| 11711917 | Seal method to integrate non-volatile memory (NVM) into logic or bipolar CMOS DMOS (BCD) technology | Cheng-Bo Shu, Yun-Chi Wu | 2023-07-25 |
| 11532637 | Embedded flash memory cell including a tunnel dielectric layer having different thicknesses over a memory region | Jui-Yu Pan, Cheng-Bo Shu, Jing-Ru Lin, Tsung-Yu Yang, Yun-Chi Wu +1 more | 2022-12-20 |
| 11349035 | Semiconductor device including non-volatile memory cells | Cheng-Bo Shu, Yun-Chi Wu | 2022-05-31 |
| 11342025 | Non-volatile memory device | Yu-Wen Tseng, Tsung-Yu Yang | 2022-05-24 |
| 11189546 | Semiconductor arrangement and method for making | Josh Lin, Yun-Chi Wu, Tsung-Yu Yang | 2021-11-30 |
| 11158647 | Memory device | Yun-Chi Wu | 2021-10-26 |
| 11121047 | Semiconductor structure | Cheng-Bo Shu, Tsung-Hua Yang | 2021-09-14 |
| 11114452 | Seal method to integrate non-volatile memory (NVM) into logic or bipolar CMOS DMOS (BCD) technology | Cheng-Bo Shu, Yun-Chi Wu | 2021-09-07 |
| 11024637 | Embedded non-volatile memory | Tsung-Yu Yang | 2021-06-01 |
| 10937795 | Seal method to integrate non-volatile memory (NVM) into logic or bipolar CMOS DMOS (BCD) technology | Cheng-Bo Shu, Yun-Chi Wu | 2021-03-02 |
| 10879257 | Integrated chip having a logic gate electrode and a tunnel dielectric layer | Jui-Yu Pan, Cheng-Bo Shu, Jing-Ru Lin, Tsung-Yu Yang, Yun-Chi Wu +1 more | 2020-12-29 |
| 10879181 | Embedded non-volatile memory with side word line | Yung Chun Tu, Tsung-Yu Yang | 2020-12-29 |
| 10720214 | Non-volatile memory device and method for controlling the non-volatile memory device | Yu-Wen Tseng, Tsung-Yu Yang | 2020-07-21 |
| 10693018 | Method of manufacturing a semiconductor device including non-volatile memory cells | Cheng-Bo Shu, Yun-Chi Wu | 2020-06-23 |
| 10665726 | Memory device and operation method thereof | Tsung-Yu Yang | 2020-05-26 |
| 10510765 | Memory device and method for fabricating the same | Yun-Chi Wu | 2019-12-17 |
| 10504912 | Seal method to integrate non-volatile memory (NVM) into logic or bipolar CMOS DMOS (BCD) technology | Cheng-Bo Shu, Yun-Chi Wu | 2019-12-10 |