Issued Patents All Time
Showing 1–25 of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12402378 | Semiconductor arrangement including first and second gate electrodes and method of manufacture | Tsung-Yu Yang, Cheng-Bo Shu, Chien-Hung Liu | 2025-08-26 |
| 12317584 | Method of forming high voltage transistor and structure resulting therefrom | Yuan-Cheng Yang, Tsu-Hsiu Perng, Shih-Jung Tu, Cheng-Bo Shu, Chia-Chen Chang | 2025-05-27 |
| 12266577 | Deep trench isolation structure and method of making the same | Hung-Ling Shih, Tsung-Yu Yang, Po-Wei Liu | 2025-04-01 |
| 12166121 | Integrated circuit structure | Cheng-Bo Shu | 2024-12-10 |
| 12165955 | Semiconductor arrangement and method for making | Josh Lin, Chung-Jen Huang, Tsung-Yu Yang | 2024-12-10 |
| 12144173 | Seal method to integrate non-volatile memory (NVM) into logic or bipolar CMOS DMOS (BCD) technology | Cheng-Bo Shu, Chung-Jen Huang | 2024-11-12 |
| 12114503 | Integrated chip including a tunnel dielectric layer which has different thicknesses over a protrusion region of a substrate | Jui-Yu Pan, Cheng-Bo Shu, Chung-Jen Huang, Jing-Ru Lin, Tsung-Yu Yang +1 more | 2024-10-08 |
| 12094984 | Semiconductor device | Cheng-Bo Shu, Chung-Jen Huang | 2024-09-17 |
| 12040397 | Gate electrode extending into a shallow trench isolation structure in high voltage devices | Yuan-Cheng Yang, Shih-Jung Tu | 2024-07-16 |
| 11990545 | Semiconductor device having fully oxidized gate oxide layer and method for making the same | Tsu-Hsiu Perng, Chia-Chen Chang, Cheng-Bo Shu, Jyun-Guan Jhou, Pei-Lun Wang | 2024-05-21 |
| 11894425 | Semiconductor arrangement and method of manufacture | Tsung-Yu Yang, Cheng-Bo Shu, Chien-Hung Liu | 2024-02-06 |
| 11854942 | Semiconductor arrangement and method for making | Josh Lin, Chung-Jen Huang, Tsung-Yu Yang | 2023-12-26 |
| 11855201 | Semiconductor structure | Chia-Ming Pan, Chia-Ta Hsieh, Po-Wei Liu | 2023-12-26 |
| 11798836 | Semiconductor isolation structure and method of making the same | Tsung-Yu Yang, Po-Wei Liu, Yu-Wen Tseng, Chia-Ta Hsieh, Ping-Cheng Li +2 more | 2023-10-24 |
| 11711917 | Seal method to integrate non-volatile memory (NVM) into logic or bipolar CMOS DMOS (BCD) technology | Cheng-Bo Shu, Chung-Jen Huang | 2023-07-25 |
| 11705515 | Gate electrode extending into a shallow trench isolation structure in high voltage devices | Yuan-Cheng Yang, Shih-Jung Tu | 2023-07-18 |
| 11688805 | Integrated circuit structure and method for forming the same | Cheng-Bo Shu | 2023-06-27 |
| 11676850 | Semiconductor device and method of manufacturing the same | Chia-Chen Chang, Yuan-Cheng Yang | 2023-06-13 |
| 11574918 | Method of manufacturing a semiconductor device and a semiconductor device | Yu-Wen Tseng | 2023-02-07 |
| 11575008 | Semiconductor arrangement and method of manufacture | Tsung-Yu Yang, Cheng-Bo Shu, Chien-Hung Liu | 2023-02-07 |
| 11532637 | Embedded flash memory cell including a tunnel dielectric layer having different thicknesses over a memory region | Jui-Yu Pan, Cheng-Bo Shu, Chung-Jen Huang, Jing-Ru Lin, Tsung-Yu Yang +1 more | 2022-12-20 |
| 11508843 | Semiconductor device having fully oxidized gate oxide layer and method for making the same | Tsu-Hsiu Perng, Chia-Chen Chang, Cheng-Bo Shu, Jyun-Guan Jhou, Pei-Lun Wang | 2022-11-22 |
| 11462639 | Semiconductor structure and method for forming the same | Chia-Ming Pan, Chia-Ta Hsieh, Po-Wei Liu | 2022-10-04 |
| 11450574 | Deep trench isolation structure and method of making the same | Hung-Ling Shih, Tsung-Yu Yang, Po-Wei Liu | 2022-09-20 |
| 11424261 | Integrated circuit with different memory gate work functions | Cheng-Bo Shu, Chien-Hung Liu | 2022-08-23 |