Issued Patents All Time
Showing 1–13 of 13 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12387786 | Bit line and word line connection for memory array | Chang-Chih Huang, Kuo-Chyuan Tzeng | 2025-08-12 |
| 12114503 | Integrated chip including a tunnel dielectric layer which has different thicknesses over a protrusion region of a substrate | Cheng-Bo Shu, Chung-Jen Huang, Jing-Ru Lin, Tsung-Yu Yang, Yun-Chi Wu +1 more | 2024-10-08 |
| 11715519 | Bit line and word line connection for memory array | Chang-Chih Huang, Kuo-Chyuan Tzeng | 2023-08-01 |
| 11532637 | Embedded flash memory cell including a tunnel dielectric layer having different thicknesses over a memory region | Cheng-Bo Shu, Chung-Jen Huang, Jing-Ru Lin, Tsung-Yu Yang, Yun-Chi Wu +1 more | 2022-12-20 |
| 11211120 | Bit line and word line connection for memory array | Chang-Chih Huang, Kuo-Chyuan Tzeng | 2021-12-28 |
| 10879257 | Integrated chip having a logic gate electrode and a tunnel dielectric layer | Cheng-Bo Shu, Chung-Jen Huang, Jing-Ru Lin, Tsung-Yu Yang, Yun-Chi Wu +1 more | 2020-12-29 |
| 10872777 | Self-aligned double patterning (SADP) method | Kuo-Chyuan Tzeng, Lee-Chuan Tseng, Ying Chen | 2020-12-22 |
| 10483119 | Self-aligned double patterning (SADP) method | Kuo-Chyuan Tzeng, Lee-Chuan Tseng, Ying Chen | 2019-11-19 |
| 10269822 | Method to fabricate uniform tunneling dielectric of embedded flash memory cell | Cheng-Bo Shu, Chung-Jen Huang, Jing-Ru Lin, Tsung-Yu Yang, Yun-Chi Wu +1 more | 2019-04-23 |
| 9799755 | Method for manufacturing memory device and method for manufacturing shallow trench isolation | Tsung-Yu Yang, Cheng-Bo Shu, Chung-Jen Huang, Jing-Ru Lin, Yun-Chi Wu +1 more | 2017-10-24 |
| 8334560 | Reverse disturb immune asymmetrical sidewall floating gate devices | Chung-Jen Hwang, Ming-Hui Shen | 2012-12-18 |
| 7335940 | Flash memory and manufacturing method thereof | I-Chun Chuang, Cheng-Yuan Hsu | 2008-02-26 |
| 7196371 | Flash memory | Cheng-Yuan Hsu, I-Chun Chuang, Chih-Wei Hung | 2007-03-27 |