Issued Patents All Time
Showing 1–25 of 31 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12402378 | Semiconductor arrangement including first and second gate electrodes and method of manufacture | Yun-Chi Wu, Tsung-Yu Yang, Chien-Hung Liu | 2025-08-26 |
| 12317584 | Method of forming high voltage transistor and structure resulting therefrom | Yuan-Cheng Yang, Yun-Chi Wu, Tsu-Hsiu Perng, Shih-Jung Tu, Chia-Chen Chang | 2025-05-27 |
| 12166121 | Integrated circuit structure | Yun-Chi Wu | 2024-12-10 |
| 12144173 | Seal method to integrate non-volatile memory (NVM) into logic or bipolar CMOS DMOS (BCD) technology | Chung-Jen Huang, Yun-Chi Wu | 2024-11-12 |
| 12114503 | Integrated chip including a tunnel dielectric layer which has different thicknesses over a protrusion region of a substrate | Jui-Yu Pan, Chung-Jen Huang, Jing-Ru Lin, Tsung-Yu Yang, Yun-Chi Wu +1 more | 2024-10-08 |
| 12094984 | Semiconductor device | Yun-Chi Wu, Chung-Jen Huang | 2024-09-17 |
| 11990545 | Semiconductor device having fully oxidized gate oxide layer and method for making the same | Tsu-Hsiu Perng, Yun-Chi Wu, Chia-Chen Chang, Jyun-Guan Jhou, Pei-Lun Wang | 2024-05-21 |
| 11894425 | Semiconductor arrangement and method of manufacture | Yun-Chi Wu, Tsung-Yu Yang, Chien-Hung Liu | 2024-02-06 |
| 11711917 | Seal method to integrate non-volatile memory (NVM) into logic or bipolar CMOS DMOS (BCD) technology | Chung-Jen Huang, Yun-Chi Wu | 2023-07-25 |
| 11688805 | Integrated circuit structure and method for forming the same | Yun-Chi Wu | 2023-06-27 |
| 11575008 | Semiconductor arrangement and method of manufacture | Yun-Chi Wu, Tsung-Yu Yang, Chien-Hung Liu | 2023-02-07 |
| 11532637 | Embedded flash memory cell including a tunnel dielectric layer having different thicknesses over a memory region | Jui-Yu Pan, Chung-Jen Huang, Jing-Ru Lin, Tsung-Yu Yang, Yun-Chi Wu +1 more | 2022-12-20 |
| 11508843 | Semiconductor device having fully oxidized gate oxide layer and method for making the same | Tsu-Hsiu Perng, Yun-Chi Wu, Chia-Chen Chang, Jyun-Guan Jhou, Pei-Lun Wang | 2022-11-22 |
| 11424261 | Integrated circuit with different memory gate work functions | Yun-Chi Wu, Chien-Hung Liu | 2022-08-23 |
| 11349035 | Semiconductor device including non-volatile memory cells | Yun-Chi Wu, Chung-Jen Huang | 2022-05-31 |
| 11121047 | Semiconductor structure | Tsung-Hua Yang, Chung-Jen Huang | 2021-09-14 |
| 11114452 | Seal method to integrate non-volatile memory (NVM) into logic or bipolar CMOS DMOS (BCD) technology | Chung-Jen Huang, Yun-Chi Wu | 2021-09-07 |
| 10937795 | Seal method to integrate non-volatile memory (NVM) into logic or bipolar CMOS DMOS (BCD) technology | Chung-Jen Huang, Yun-Chi Wu | 2021-03-02 |
| 10879257 | Integrated chip having a logic gate electrode and a tunnel dielectric layer | Jui-Yu Pan, Chung-Jen Huang, Jing-Ru Lin, Tsung-Yu Yang, Yun-Chi Wu +1 more | 2020-12-29 |
| 10879258 | Memory cell comprising a metal control gate with a work function for an enlarged operation window | Yun-Chi Wu, Chien-Hung Liu | 2020-12-29 |
| 10840333 | Semiconductor arrangement and method of manufacture | Yun-Chi Wu, Tsung-Yu Yang, Chien-Hung Liu | 2020-11-17 |
| 10693018 | Method of manufacturing a semiconductor device including non-volatile memory cells | Yun-Chi Wu, Chung-Jen Huang | 2020-06-23 |
| 10672783 | Integrated circuit and method for manufacturing the same | Yun-Chi Wu, Chien-Hung Liu | 2020-06-02 |
| 10510767 | Integrated circuit and method for manufacturing the same | Yun-Chi Wu, Chien-Hung Liu | 2019-12-17 |
| 10504912 | Seal method to integrate non-volatile memory (NVM) into logic or bipolar CMOS DMOS (BCD) technology | Chung-Jen Huang, Yun-Chi Wu | 2019-12-10 |