Issued Patents All Time
Showing 25 most recent of 72 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12277977 | ONON sidewall structure for memory device and method for making the same | Chen-Ming Huang, Wen-Tuo Huang, Yu-Hsiang Yang, Yu-Ling Hsu, Wei-Lin Chang +5 more | 2025-04-15 |
| 12191282 | Shared pad/bridge layout for a 3D IC | Harry-Hak-Lay Chuang, Wei-Cheng Wu, Wen-Tuo Huang, Wei Chuang Wu, Shih Kuang Yang +5 more | 2025-01-07 |
| 12101931 | Strap-cell architecture for embedded memory | Wen-Tuo Huang, Ping-Cheng Li, Hung-Ling Shih, Po-Wei Liu, Yu-Ling Hsu +2 more | 2024-09-24 |
| 12068032 | Device-region layout for embedded flash | Shih Kuang Yang, Ping-Cheng Li, Hung-Ling Shih, Po-Wei Liu, Wen-Tuo Huang +2 more | 2024-08-20 |
| 12009033 | ONON sidewall structure for memory device and method for making the same | Chen-Ming Huang, Wen-Tuo Huang, Yu-Hsiang Yang, Yu-Ling Hsu, Wei-Lin Chang +5 more | 2024-06-11 |
| 11973095 | Method for forming chip package with second opening surrounding first opening having conductive structure therein | Kuei-Wei Chen, Chia-Ming Cheng | 2024-04-30 |
| 11942563 | Manufacturing method of chip package and chip package | Hui-Hsien Wu, Jian-Hong Chen, Tsang-Yu Liu, Kuei-Wei Chen | 2024-03-26 |
| 11869951 | Control gate strap layout to improve a word line etch process window | Yu-Ling Hsu, Ping-Cheng Li, Hung-Ling Shih, Po-Wei Liu, Wen-Tuo Huang +2 more | 2024-01-09 |
| 11854621 | ONON sidewall structure for memory device and methods of making the same | Chen-Ming Huang, Wen-Tuo Huang, ShihKuang Yang, Yu-Chun Chang, Shih-Hsien Chen +5 more | 2023-12-26 |
| 11851910 | Lock | — | 2023-12-26 |
| 11785770 | Strap-cell architecture for embedded memory | Wen-Tuo Huang, Ping-Cheng Li, Hung-Ling Shih, Po-Wei Liu, Yu-Ling Hsu +2 more | 2023-10-10 |
| 11705368 | Manufacturing method of chip package and chip package | Hui-Hsien Wu, Jian-Hong Chen, Tsang-Yu Liu, Kuei-Wei Chen | 2023-07-18 |
| 11699488 | Device-region layout for embedded flash | Shih Kuang Yang, Ping-Cheng Li, Hung-Ling Shih, Po-Wei Liu, Wen-Tuo Huang +2 more | 2023-07-11 |
| 11552087 | Strap-cell architecture for embedded memory | Wen-Tuo Huang, Ping-Cheng Li, Hung-Ling Shih, Po-Wei Liu, Yu-Ling Hsu +2 more | 2023-01-10 |
| 11450697 | Chip package with substrate having first opening surrounded by second opening and method for forming the same | Kuei-Wei Chen, Chia-Ming Cheng | 2022-09-20 |
| 11306514 | Connection lock | — | 2022-04-19 |
| 11306505 | Lock | — | 2022-04-19 |
| 11158377 | Device-region layout for embedded flash | Shih Kuang Yang, Ping-Cheng Li, Hung-Ling Shih, Po-Wei Liu, Wen-Tuo Huang +2 more | 2021-10-26 |
| 11127827 | Control gate strap layout to improve a word line etch process window | Yu-Ling Hsu, Ping-Cheng Li, Hung-Ling Shih, Po-Wei Liu, Wen-Tuo Huang +2 more | 2021-09-21 |
| 11121031 | Manufacturing method of chip package and chip package | Hui-Hsien Wu, Jian-Hong Chen, Tsang-Yu Liu, Kuei-Wei Chen | 2021-09-14 |
| 10943913 | Strap-cell architecture for embedded memory | Wen-Tuo Huang, Ping-Cheng Li, Hung-Ling Shih, Po-Wei Liu, Yu-Ling Hsu +2 more | 2021-03-09 |
| 10861553 | Device-region layout for embedded flash | Shih Kuang Yang, Ping-Cheng Li, Hung-Ling Shih, Po-Wei Liu, Wen-Tuo Huang +2 more | 2020-12-08 |
| 10461117 | Semiconductor structure and method for manufacturing semiconductor structure | Yen-Shih Ho, Tsang-Yu Liu, Chaung-Lin LAI | 2019-10-29 |
| 10233676 | Connection lock | — | 2019-03-19 |
| 10153237 | Chip package and method for forming the same | Yen-Shih Ho, Po-Han Lee, Wei-Luen SUEN | 2018-12-11 |