Issued Patents All Time
Showing 51–75 of 131 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9761677 | Gate contact structure of FinFET | Chi-Wen Liu | 2017-09-12 |
| 9754842 | FinFET with dummy gate on non-recessed shallow trench isolation (STI) | Chi-Wen Liu | 2017-09-05 |
| 9741810 | Strained channel of gate-all-around transistor | Kuo-Cheng Ching, Chi-Wen Liu | 2017-08-22 |
| 9711463 | Dicing method for power transistors | Yu-Syuan Lin, Jiun-Lei Jerry Yu, Ming-Cheng Lin, Hsin-Chieh Huang | 2017-07-18 |
| 9698026 | Systems and methods for annealing semiconductor structures | Chun Hsiung Tsai, Zi-Wei Fang | 2017-07-04 |
| 9691621 | Silicide region of gate-all-around transistor | Kuo-Cheng Ching, Chi-Wen Liu | 2017-06-27 |
| 9685369 | Contact etch stop layers of a field effect transistor | Chi-Wen Liu | 2017-06-20 |
| 9673280 | Cobalt silicidation process for substrates comprised with a silicon-germanium layer | Chien-Chao Huang, Yee-Chia Yeo, Chun-Chieh Lin, Chenming Hu | 2017-06-06 |
| 9640487 | Wafer alignment mark scheme | Wei-Hsiang Tseng, Chin-Hsiang Lin, Heng-Hsin Liu, Ho-Ping Chen, Jui-Chun Peng | 2017-05-02 |
| 9570493 | Dielectric grid bottom profile for light focusing | Yun-Wei Cheng, Horng-Huei Tseng, Chun-Hao Chou, Tsung-Han Tsai, Kuo-Cheng Lee +1 more | 2017-02-14 |
| 9520498 | FinFET structure and method for fabricating the same | Kuo-Cheng Ching, Guan-Lin Chen, Chi-Wen Liu | 2016-12-13 |
| 9508839 | Short-gate tunneling field effect transistor having non-uniformly doped vertical channel and fabrication method thereof | Ru Huang, Chunlei Wu, Qianqian Huang, Jiaxin Wang, Yangyuan Wang | 2016-11-29 |
| 9508603 | Formation of nickel silicon and nickel germanium structure at staggered times | Chi-Wen Liu | 2016-11-29 |
| 9496397 | FinFet device with channel epitaxial region | Kuo-Cheng Ching, Zhi-Chang Lin, Chi-Wen Liu | 2016-11-15 |
| 9455334 | Method of forming a Fin structure of semiconductor device | Kuo-Cheng Ching, Jiun-Jia Huang, Chi-Wen Liu | 2016-09-27 |
| 9418871 | Systems and methods for annealing semiconductor structures | Chun Hsiung Tsai, Zi-Wei Fang | 2016-08-16 |
| 9406669 | Method and structure for vertical tunneling field effect transistor and planar devices | Harry-Hak-Lay Chuang, Yi-Ren Chen, Chi-Wen Liu, Ming Zhu | 2016-08-02 |
| 9397159 | Silicide region of gate-all-around transistor | Kuo-Cheng Ching, Chi-Wen Liu | 2016-07-19 |
| 9385069 | Gate contact structure for FinFET | Chi-Wen Liu | 2016-07-05 |
| 9337318 | FinFET with dummy gate on non-recessed shallow trench isolation (STI) | Chi-Wen Liu | 2016-05-10 |
| 9338834 | Systems and methods for microwave-radiation annealing | Chun Hsiung Tsai, Zi-Wei Fang | 2016-05-10 |
| 9331075 | Systems and methods for fabricating semiconductor devices at different levels | Chi-Wen Liu | 2016-05-03 |
| 9331179 | Metal gate and gate contact structure for FinFET | Chi-Wen Liu | 2016-05-03 |
| 9318431 | Integrated circuit having a MOM capacitor and method of making same | Chi-Wen Liu | 2016-04-19 |
| 9312363 | Multi-fin device and method of making same | Chi-Wen Liu | 2016-04-12 |