Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9335827 | Gesture input systems and methods using 2D sensors | Chih-Hao Huang, Chih-Pin Liao, Pin-Hong Liou | 2016-05-10 |
| 9268408 | Operating area determination method and system | Chia-Te Chou, Shou-Te Wei, Chih-Hsuan Lee | 2016-02-23 |
| 9003435 | Method of recommending media content and media playing system thereof | Hsi-Chun Hsiao, Shou-Te Wei | 2015-04-07 |
| 8937589 | Gesture control method and gesture control device | Shou-Te Wei, Chia-Te Chou, Chih-Pin Liao | 2015-01-20 |
| 7663185 | FIN-FET device structure formed employing bulk semiconductor substrate | Kuang-Hsin Chen, Jhi-Cherng Lu, Chuan-Ping Hou, Peng-Fu Hsu, Hung-Wei Chen +1 more | 2010-02-16 |
| 7638376 | Method for forming SOI device | Cheng-Kuo Wen, Chien-Chao Huang, Hao Chen, Fu-Liang Yang | 2009-12-29 |
| 7633127 | Silicide gate transistors and method of manufacture | Cheng-Kuo Wen, Yee-Chia Yeo | 2009-12-15 |
| 7538351 | Method for forming an SOI structure with improved carrier mobility and ESD protection | Hung-Wei Chen, Kuang-Hsin Chen, Di-Hong Lee | 2009-05-26 |
| 7332777 | STI liner for SOI structure | Kuang-Hsin Chen, Hung-Wei Chen, Di-Hong Lee, Chuan-Ping Hou, Jhi-Cherng Lu | 2008-02-19 |
| 7205601 | FinFET split gate EEPROM structure and method of its fabrication | Di-Hong Lee, Kuang-Hsin Chen, Hung-Wei Chen | 2007-04-17 |
| 7183150 | Resist protect oxide structure of sub-micron salicide process | Ming-Chang Hsieh, Hung-Chih Tsai, Pin-Shyne Chin | 2007-02-27 |
| 7067379 | Silicide gate transistors and method of manufacture | Cheng-Kuo Wen, Yee-Chia Yeo | 2006-06-27 |
| 7053453 | Substrate contact and method of forming the same | Chien-Chao Huang, Fu-Liang Yang | 2006-05-30 |
| 7026196 | Method of forming field effect transistor and structure formed thereby | Chuan-Ping Hou, Jhi-Cherng Lu, Kuang-Hsin Chen | 2006-04-11 |
| 6979867 | SOI chip with mesa isolation and recess resistant regions | Yee-Chia Yeo, Hao Chen, Fu-Liang Yang, Chenming Hu | 2005-12-27 |
| 6955955 | STI liner for SOI structure | Kuang-Hsin Chen, Hung-Wei Chen, Di-Hong Lee, Chuan-Ping Hou, Jhi-Cherng Lu | 2005-10-18 |
| 6864149 | SOI chip with mesa isolation and recess resistant regions | Yee-Chia Yeo, Hao Chen, Fu-Liang Yang, Chenming Hu | 2005-03-08 |
| 6815274 | Resist protect oxide structure of sub-micron salicide process | Ming-Chang Hsieh, Hung-Chih Tsai, Pin-Shyne Chin | 2004-11-09 |
| 6191018 | Method for selective resistivity adjustment of polycide lines for enhanced design flexibility and improved space utilization in sub-micron integrated circuits | Wen-Jye Yue, Tzong-Sheng Chang | 2001-02-20 |