Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8865539 | Fully depleted SOI multiple threshold voltage application | Hao Chen, Chang-Yun Chang, Fu-Liang Yang | 2014-10-21 |
| 7663185 | FIN-FET device structure formed employing bulk semiconductor substrate | Kuang-Hsin Chen, Hsun-Chih Tsao, Jhi-Cherng Lu, Chuan-Ping Hou, Peng-Fu Hsu +1 more | 2010-02-16 |
| 7538351 | Method for forming an SOI structure with improved carrier mobility and ESD protection | Hung-Wei Chen, Hsun-Chih Tsao, Kuang-Hsin Chen | 2009-05-26 |
| 7452778 | Semiconductor nano-wire devices and methods of fabrication | Hung-Wei Chen, Yee-Chia Yeo, Fu-Liang Yang, Chenming Hu | 2008-11-18 |
| 7382023 | Fully depleted SOI multiple threshold voltage application | Hao Chen, Chang-Yun Chang, Fu-Liang Yang | 2008-06-03 |
| 7332777 | STI liner for SOI structure | Kuang-Hsin Chen, Hsun-Chih Tsao, Hung-Wei Chen, Chuan-Ping Hou, Jhi-Cherng Lu | 2008-02-19 |
| 7265425 | Semiconductor device employing an extension spacer and a method of forming the same | Kuang-Hsin Chen, Tang-Xuan Zhong, Chien-Chao Huang, Cheng-Kuo Wen | 2007-09-04 |
| 7205601 | FinFET split gate EEPROM structure and method of its fabrication | Hsun-Chih Tsao, Kuang-Hsin Chen, Hung-Wei Chen | 2007-04-17 |
| 6955955 | STI liner for SOI structure | Kuang-Hsin Chen, Hsun-Chih Tsao, Hung-Wei Chen, Chuan-Ping Hou, Jhi-Cherng Lu | 2005-10-18 |