Issued Patents All Time
Showing 1–25 of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11940737 | Method of fabricating reticle | Hsueh-Yi Chung, Yung-Cheng Chen, Fei-Gwo Tsai, Chi-Hung Liao, Shih-Chi Fu +4 more | 2024-03-26 |
| 11653503 | Semiconductor structure with data storage structure and method for manufacturing the same | Woan-Yun HSIAO, Huang-Kui Chen, Ya-Chin King, Chrong-Jung Lin | 2023-05-16 |
| 11011419 | Method for forming interconnect structure | Bor-Zen Tien, Jhu-Ming Song, Hsuan-Han Lin, Kuang-Hsin Chen, Mu-Yi Lin | 2021-05-18 |
| 11003091 | Method of fabricating reticle | Hsueh-Yi Chung, Yung-Cheng Chen, Fei-Gwo Tsai, Chi-Hung Liao, Shih-Chi Fu +4 more | 2021-05-11 |
| 10957653 | Methods for manufacturing semiconductor arrangements using photoresist masks | Tsung-Yu Chiang, Chen Kuang-Hsin, Bor-Zen Tien | 2021-03-23 |
| 10763305 | Semiconductor structure with data storage structure | Woan-Yun HSIAO, Huang-Kui Chen, Ya-Chin King, Chrong-Jung Lin | 2020-09-01 |
| 10629481 | Method for forming interconnect structure | Bor-Zen Tien, Jhu-Ming Song, Hsuan-Han Lin, Kuang-Hsin Chen, Mu-Yi Lin | 2020-04-21 |
| 10534272 | Method of fabricating reticle | Hsueh-Yi Chung, Yung-Cheng Chen, Fei-Gwo Tsai, Chi-Hung Liao, Shih-Chi Fu +4 more | 2020-01-14 |
| 10515902 | Back-end-of-line (BEOL) arrangement with multi-height interlayer dielectric (ILD) structures | Tsung-Yu Chiang, Chen Kuang-Hsin, Bor-Zen Tien | 2019-12-24 |
| 10090360 | Method of manufacturing a semiconductor structure including a plurality of trenches | Woan-Yun HSIAO, Ya-Chin King, Chrong-Jung Lin, Huang-Kui Chen | 2018-10-02 |
| 10073354 | Exposure method of wafer substrate, manufacturing method of semiconductor device, and exposure tool | Hsueh-Yi Chung, Yung-Cheng Chen, Fei-Gwo Tsai, Chi-Hung Liao, Shih-Chi Fu +4 more | 2018-09-11 |
| 9870998 | Semiconductor arrangement having an overlay alignment mark with a height shorter than a neighboring gate structure | Tsung-Yu Chiang, Chen Kuang-Hsin, Bor-Zen Tien | 2018-01-16 |
| 9831130 | Method for forming semiconductor device structure | An-Lun Lo, Wei-Shuo Ho, Chrong-Jung Lin, Ya-Chin King | 2017-11-28 |
| 9716034 | Method for forming interconnect structure | Bor-Zen Tien, Jhu-Ming Song, Hsuan-Han Lin, Kuang-Hsin Chen, Mu-Yi Lin | 2017-07-25 |
| 9679818 | Semiconductor device structure and method for forming the same | An-Lun Lo, Wei-Shuo Ho, Chrong-Jung Lin, Ya-Chin King | 2017-06-13 |
| 9508590 | Methods and apparatus of metal gate transistors | Tsung-Yu Chiang, Kuang-Hsin Chen, Bor-Zen Tien | 2016-11-29 |
| 9252259 | Methods and apparatus of metal gate transistors | Tsung-Yu Chiang, Kuang-Hsin Chen, Bor-Zen Tien | 2016-02-02 |
| 9190319 | Method for forming interconnect structure | Hsuan-Han Lin, Jhu-Ming Song, Mu-Yi Lin, Kuang-Hsin Chen, Bor-Zen Tien | 2015-11-17 |
| 9178066 | Methods for forming a semiconductor arrangement with structures having different heights | Tsung-Yu Chiang, Chen Kuang-Hsin, Bor-Zen Tien | 2015-11-03 |
| 9122828 | Apparatus and method for designing an integrated circuit layout having a plurality of cell technologies | Tsung-Yu Chiang, Kuang-Hsin Chen, Song-Bor Lee, Bor-Zen Tien | 2015-09-01 |
| 8860151 | Semiconductor device having a spacer and a liner overlying a sidewall of a gate structure and method of forming the same | Sheng-Ching Chen, Kuang-Hsin Chen, Bor-Zen Tien | 2014-10-14 |
| 8741726 | Reacted layer for improving thickness uniformity of strained structures | Cheng-Te Lin, Chih-Lin Wang, Yi-Huang Wu | 2014-06-03 |
| 7998772 | Method to reduce leakage in a protection diode structure | Bor-Zen Tien, Yung-Fu Shen, Jieh-Ting Chang | 2011-08-16 |
| 7663164 | Semiconductor device with reduced leakage protection diode | Bor-Zen Tien, Yung-Fu Shen, Jieh-Ting Chang | 2010-02-16 |
| 7015129 | Bond pad scheme for Cu process | Chia-Hung Lai, Jiunn-Jyi Lin, Min Cao, Huan Chi Tseng, Yu-Hua Lee +1 more | 2006-03-21 |