Issued Patents All Time
Showing 26–36 of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6844626 | Bond pad scheme for Cu process | Chia-Hung Lai, Jiunn-Jyi Lin, Min Cao, Huan Chi Tseng, Yu-Hua Lee +1 more | 2005-01-18 |
| 6348389 | Method of forming and etching a resist protect oxide layer including end-point etch | Chen Cheng Chou | 2002-02-19 |
| 6346449 | Non-distort spacer profile during subsequent processing | Shih-Chang Huang, Bor-Zen Tien, Chen Cheng Chou | 2002-02-12 |
| 6294448 | Method to improve TiSix salicide formation | Hung-Chi Tsai, Bor-Zen Tien | 2001-09-25 |
| 6284611 | Method for salicide process using a titanium nitride barrier layer | Bor-Zen Tien, Chen Cheng Chou, Wen-Jye Yue | 2001-09-04 |
| 6191018 | Method for selective resistivity adjustment of polycide lines for enhanced design flexibility and improved space utilization in sub-micron integrated circuits | Wen-Jye Yue, Hsun-Chih Tsao | 2001-02-20 |
| 6004841 | Fabrication process for MOSFET devices and a reproducible capacitor structure | Chen Cheng Chou | 1999-12-21 |
| 6004829 | Method of increasing end point detection capability of reactive ion etching by adding pad area | Yen-Shih Ho, Ruey-Hsin Liou, Yuan Yu | 1999-12-21 |
| 5817562 | Method for making improved polysilicon FET gate electrode structures and sidewall spacers for more reliable self-aligned contacts (SAC) | Chen Cheng Chou, Jenn Tsao | 1998-10-06 |
| 5807786 | Method of making a barrier layer to protect programmable antifuse structure from damage during fabrication sequence | — | 1998-09-15 |
| 5792681 | Fabrication process for MOSFET devices and a reproducible capacitor structure | Chen Cheng Chou | 1998-08-11 |