Issued Patents All Time
Showing 1–25 of 44 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7482278 | Key-hole free process for high aspect ratio gap filling with reentrant spacer | Tze-Liang Ying, James Wu, Wen-Chuan Chiang | 2009-01-27 |
| 7160811 | Laminated silicate glass layer etch stop method for fabricating microelectronic product | Yen-Ming Chen, Huan Chi Tseng, Dian-Hau Chen, Chia-Hung Lai, Kang-Min Kuo | 2007-01-09 |
| 7056821 | Method for manufacturing dual damascene structure with a trench formed first | Chin-Tien Yang, Juan-Jann Jou, Chia-Hung Lai | 2006-06-06 |
| 7015129 | Bond pad scheme for Cu process | Chia-Hung Lai, Jiunn-Jyi Lin, Tzong-Sheng Chang, Min Cao, Huan Chi Tseng +1 more | 2006-03-21 |
| 6956254 | Multilayered dual bit memory device with improved write/erase characteristics and method of manufacturing | Chin-Tien Yang, Mu-Yi Lin, Yu-Wei Tseng, Min Ca | 2005-10-18 |
| 6844626 | Bond pad scheme for Cu process | Chia-Hung Lai, Jiunn-Jyi Lin, Tzong-Sheng Chang, Min Cao, Huan Chi Tseng +1 more | 2005-01-18 |
| 6600228 | Keyhole at the top metal level prefilled with photoresist to prevent passivation damage even for a severe top metal rule | Min-Hsiung Chiang, Jenn Ming Huang | 2003-07-29 |
| 6586162 | Simple photo development step to form TiSix gate in DRAM process | — | 2003-07-01 |
| 6555435 | Method to eliminate shorts between adjacent contacts due to interlevel dielectric voids | Ming-Hsiung Chiang, James Wu | 2003-04-29 |
| 6436763 | Process for making embedded DRAM circuits having capacitor under bit-line (CUB) | Jenn Ming Huang, Cheng-Ming Wu | 2002-08-20 |
| 6403416 | Method for making a double-cylinder-capacitor structure for dynamic random access memory (DRAM) | Kuo-Ching Huang, James Wu, Wen-Chuan Chiang | 2002-06-11 |
| 6365464 | Method to eliminate shorts between adjacent contacts due to interlevel dielectric voids | Ming-Hsiung Chiang, James Wu | 2002-04-02 |
| 6323118 | Borderless dual damascene contact | Cheng-Yeh Shih, James Wu | 2001-11-27 |
| 6307213 | Method for making a fuse structure for improved repaired yields on semiconductor memory devices | Kuo-Ching Huang, Tse-Liang Ying, Cheng-Yeh Shih, Cheng-Ming Wu | 2001-10-23 |
| 6294456 | Method of prefilling of keyhole at the top metal level with photoresist to prevent passivation damage even for a severe top metal rule | Min-Hsiung Chiang, Jenn Ming Huang | 2001-09-25 |
| 6274426 | Self-aligned contact process for a crown shaped dynamic random access memory capacitor structure | James Wu, Min-Hsiung Chiang | 2001-08-14 |
| 6265315 | Method for improving chemical/mechanical polish uniformity over rough topography for semiconductor integrated circuits | James Wu | 2001-07-24 |
| 6235580 | Process for forming a crown shaped capacitor structure for a DRAM device | Cheng-Ming Wu, Wen-Chuan Chiang | 2001-05-22 |
| 6228736 | Modified method for forming cylinder-shaped capacitors for dynamic random access memory (DRAM) | James Wu | 2001-05-08 |
| 6194234 | Method to evaluate hemisperical grain (HSG) polysilicon surface | Kuo-Ching Huang, Tse-Liang Ying, Wen-Chuan Chiang | 2001-02-27 |
| 6187659 | Node process integration technology to improve data retention for logic based embedded dram | Tse-Liang Ying, Wen-Chuan Chiang, Cheng-Ming Wu | 2001-02-13 |
| 6165839 | Process to fabricate a cylindrical, capacitor structure under a bit line structure for a dynamic random access memory cell | Cheng-Ming Wu, Wen-Chuan Chiang | 2000-12-26 |
| 6162686 | Method for forming a fuse in integrated circuit application | Kuo-Ching Huang, Tse-Liang Ying, Ming Li | 2000-12-19 |
| 6136695 | Method for fabricating a self-aligned contact | Cheng-Ming Wu, Ming-Hsiung Chiang | 2000-10-24 |
| 6121073 | Method for making a fuse structure for improved repaired yields on semiconductor memory devices | Kuo-Ching Huang, Tse-Liang Ying, Cheng-Yeh Shih, Cheng-Ming Wu | 2000-09-19 |