Issued Patents All Time
Showing 1–25 of 68 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7119017 | Method for improving interlevel dielectric gap filling over semiconductor structures having high aspect ratios | An-Chun Tu | 2006-10-10 |
| 7037776 | Single polysilicon process for DRAM | Chen-Yong Lin | 2006-05-02 |
| 7030440 | Single poly-si process for DRAM by deep N-well (NW) plate | — | 2006-04-18 |
| 6825078 | Single poly-Si process for DRAM by deep N well (NW) plate | — | 2004-11-30 |
| 6818495 | Method for forming high purity silicon oxide field oxide isolation region | Min-Hsiung Chiang, Jin-Yuan Lee | 2004-11-16 |
| 6617631 | Method for making closely spaced capacitors with reduced parasitic capacitance on a dynamic random access memory (DRAM) device | — | 2003-09-09 |
| 6600228 | Keyhole at the top metal level prefilled with photoresist to prevent passivation damage even for a severe top metal rule | Yu-Hua Lee, Min-Hsiung Chiang | 2003-07-29 |
| 6579784 | Method for forming a metal gate integrated with a source and drain salicide process with oxynitride spacers | — | 2003-06-17 |
| 6436763 | Process for making embedded DRAM circuits having capacitor under bit-line (CUB) | Yu-Hua Lee, Cheng-Ming Wu | 2002-08-20 |
| 6406987 | Method for making borderless contacts to active device regions and overlaying shallow trench isolation regions | — | 2002-06-18 |
| 6353269 | Method for making cost-effective embedded DRAM structures compatible with logic circuit processing | — | 2002-03-05 |
| 6351016 | Technology for high performance buried contact and tungsten polycide gate integration | Kuo-Ching Huang, Shou-Gwo Wuu, Dun-Nian Yaung | 2002-02-26 |
| 6294456 | Method of prefilling of keyhole at the top metal level with photoresist to prevent passivation damage even for a severe top metal rule | Yu-Hua Lee, Min-Hsiung Chiang | 2001-09-25 |
| 6274471 | Method for making high-aspect-ratio contacts on integrated circuits using a borderless pre-opened hard-mask technique | — | 2001-08-14 |
| 6265120 | Geometry design of active region to improve junction breakdown and field isolation in STI process | — | 2001-07-24 |
| 6255160 | Cell design and process for making dynamic random access memory (DRAM) having one or more Gigabits of memory cells | — | 2001-07-03 |
| 6251726 | Method for making an enlarged DRAM capacitor using an additional polysilicon plug as a center pillar | — | 2001-06-26 |
| 6235593 | Self aligned contact using spacers on the ILD layer sidewalls | — | 2001-05-22 |
| 6228699 | Cross leakage of capacitors in DRAM or embedded DRAM | — | 2001-05-08 |
| 6221713 | Approach for self-aligned contact and pedestal | — | 2001-04-24 |
| 6198173 | SRAM with improved Beta ratio | — | 2001-03-06 |
| 6187624 | Method for making closely spaced capacitors with reduced parasitic capacitance on a dynamic random access memory (DRAM) device | — | 2001-02-13 |
| 6159786 | Well-controlled CMP process for DRAM technology | Min-Hsiung Chiang, James C. Wu | 2000-12-12 |
| 6157064 | Method and a deep sub-micron field effect transistor structure for suppressing short channel effects | — | 2000-12-05 |
| 6137179 | Method for fabricating capacitor-over-bit line (COB) dynamic random access memory (DRAM) using tungsten landing plug contacts and TI/TIN bit lines | — | 2000-10-24 |