Issued Patents All Time
Showing 26–50 of 68 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6127260 | Method of forming a tee shaped tungsten plug structure to avoid high aspect ratio contact holes in embedded DRAM devices | — | 2000-10-03 |
| 6117725 | Method for making cost-effective embedded DRAM structures compatible with logic circuit processing | — | 2000-09-12 |
| 6117723 | Salicide integration process for embedded DRAM devices | — | 2000-09-12 |
| 6103622 | Silicide process for mixed mode product with dual layer capacitor and polysilicon resistor which is protected with a capacitor protective oxide during silicidation of FET device | — | 2000-08-15 |
| 6103621 | Silicide process for mixed mode product with dual layer capacitor which is protected by a capacitor protective oxide during silicidation of FET device | — | 2000-08-15 |
| 6100118 | Fabrication of metal fuse design for redundancy technology having a guard ring | Cheng-Yeh Shih | 2000-08-08 |
| 6100116 | Method to form a protected metal fuse | Yu-Hua Lee, James C. Wu, Cheng-Yeh Shih, Min-Hsiung Chiang | 2000-08-08 |
| 6096595 | Integration of a salicide process for MOS logic devices, and a self-aligned contact process for MOS memory devices | — | 2000-08-01 |
| 6093640 | Overlay measurement improvement between damascene metal interconnections | Jung-Hsien Hsu | 2000-07-25 |
| 6074908 | Process for making merged integrated circuits having salicide FETS and embedded DRAM circuits | — | 2000-06-13 |
| 6042999 | Robust dual damascene process | Cheng-Tung Lin, Yu-Hua Lee, Cheng-Ming Wu | 2000-03-28 |
| 6037222 | Method for fabricating a dual-gate dielectric module for memory embedded logic using salicide technology and polycide technology | Kuo-Ching Huang, Tse-Liang Ying, Chen-Jong Wang | 2000-03-14 |
| 6037199 | SOI device for DRAM cells beyond gigabit generation and method for making the same | Jin-Yuan Lee | 2000-03-14 |
| 6033999 | Method of solving contact oblique problems of an ILD layer using a rapid thermal anneal | Jann-Ming Wu, Min-Hsiung Chiang, Ming-Ta Lei | 2000-03-07 |
| 6033963 | Method of forming a metal gate for CMOS devices using a replacement gate process | Chi-Wen Su, Chung-Cheng Wu, Shui-Hung Chen | 2000-03-07 |
| 6025279 | Method of reducing nitride and oxide peeling after planarization using an anneal | Min-Hsiung Chiang, Chen-Jong Wang | 2000-02-15 |
| 6015735 | Method for forming a multi-anchor DRAM capacitor and capacitor formed | Shau-Lin Shue, Hun-Jan Tao, Chia-Shiung Tsai | 2000-01-18 |
| 6015730 | Integration of SAC and salicide processes by combining hard mask and poly definition | Chen-Jong Wang, Chue-San Yoo | 2000-01-18 |
| 6004843 | Process for integrating a MOS logic device and a MOS memory device on a single semiconductor chip | — | 1999-12-21 |
| 6001721 | Silicide and salicide on the same chip | — | 1999-12-14 |
| 5998269 | Technology for high performance buried contact and tungsten polycide gate integration | Kuo-Ching Huang, Shou-Gwo Wuu, Dun-Nian Yaung | 1999-12-07 |
| 5998252 | Method of salicide and sac (self-aligned contact) integration | — | 1999-12-07 |
| 5989966 | Method and a deep sub-micron field effect transistor structure for suppressing short channel effects | — | 1999-11-23 |
| 5989954 | Method for forming a cylinder capacitor in the dram process | Yu-Hua Lee | 1999-11-23 |
| 5963839 | Reduction of polysilicon contact resistance by nitrogen implantation | — | 1999-10-05 |