Issued Patents All Time
Showing 1–25 of 49 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8018000 | Electrostatic discharge protection pattern for high voltage applications | Jian-Hsing Lee, Yung-Tien Tsai, Anthony Oates | 2011-09-13 |
| 7826193 | String contact structure for high voltage ESD | Dah-Jyh Perng, Jian-Hsing Lee, Huang Yung-Sheng | 2010-11-02 |
| 7508639 | Input/output devices with robustness of ESD protection | Yi-Hsun Wu, Jian-Hsing Lee | 2009-03-24 |
| 7462885 | ESD structure for high voltage ESD protection | Jian-Hsing Lee, Yi-Hsun Wu, D. J. Perng, Anthony Oates | 2008-12-09 |
| 7256975 | ESD protection circuit and method | Yi-Hsun Wu, Jian-Hsing Lee | 2007-08-14 |
| 7247543 | Decoupling capacitor | Jiaw-Ren Shih, Jian-Hsing Lee | 2007-07-24 |
| 7122857 | Multi-level (4state/2-bit) stacked gate flash memory cell | Chrong-Jung Lin, Hsin-Ming Chen | 2006-10-17 |
| 7078772 | Whole chip ESD protection | Yi-Hsu Wu, Jian-Hsing Lee | 2006-07-18 |
| 6992361 | Deep well implant structure providing latch-up resistant CMOS semiconductor product | Jiaw-Ren Shin, Jian-Hsing Lee | 2006-01-31 |
| 6937457 | Decoupling capacitor | Jiaw-Ren Shih, Jian-Hsing Lee | 2005-08-30 |
| 6888248 | Extended length metal line for improved ESD performance | Jian-Hsing Lee, Jiaw-Ren Shih | 2005-05-03 |
| 6879203 | Whole chip ESD protection | Yi-Hsu Wu, Jian-Hsing Lee | 2005-04-12 |
| 6876041 | ESD protection component | Jian-Hsing Lee, Kuo-Reay Peng | 2005-04-05 |
| 6838725 | Step-shaped floating poly-si gate to improve a gate coupling ratio for flash memory application | Chrong-Jung Lin | 2005-01-04 |
| 6762439 | Diode for power protection | Jian-Hsing Lee, Jiaw-Ren Shih, Ta-Lee Yu | 2004-07-13 |
| 6756642 | Integrated circuit having improved ESD protection | Jian-Hsing Lee, Ta-Lee Yu | 2004-06-29 |
| 6734055 | Multi-level (4 state/2-bit) stacked gate flash memory cell | Chrong-Jung Lin, Hsin-Ming Chen | 2004-05-11 |
| 6730968 | Whole chip ESD protection | Yi-Hsu Wu, Jian-Hsing Lee | 2004-05-04 |
| 6645820 | Polycrystalline silicon diode string for ESD protection of different power supply connections | Kuo-Reay Peng, Jian-Hsing Lee | 2003-11-11 |
| 6614078 | Highly latchup-immune CMOS I/O structures | Jian-Hsing Lee, Jiaw-Ren Shih, Ping Lung Liao | 2003-09-02 |
| 6614693 | Combination erase waveform to reduce oxide trapping centers generation rate of flash EEPROM | Jian-Hsing Lee, Kuo-Reay Peng, Jiaw-Ren Shih | 2003-09-02 |
| 6583466 | Vertical split gate flash memory device in an orthogonal array of rows and columns with devices in columns having shared source regions | Chrong-Jung Lin, Di-Son Kuo | 2003-06-24 |
| 6552372 | Integrated circuit having improved ESD protection | Yi-Hsun Wu, Jian-Hsing Lee, Jian-Ren Shih | 2003-04-22 |
| 6548856 | Vertical stacked gate flash memory device | Chrong-Jung Lin, Mong-Song Liang | 2003-04-15 |
| 6541824 | Modified source side inserted anti-type diffusion ESD protection device | Jian-Hsing Lee, Jiaw-Ren Shih, Yi-Hsun Wu | 2003-04-01 |