Issued Patents All Time
Showing 26–49 of 49 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6437397 | Flash memory cell with vertically oriented channel | Chrong-Jung Lin, Jong Chen, Di-Son Kuo | 2002-08-20 |
| 6420221 | Method of manufacturing a highly latchup-immune CMOS I/O structure | Jian-Hsing Lee, Jiaw-Ren Shih, Ping Lung Liao | 2002-07-16 |
| 6391719 | Method of manufacture of vertical split gate flash memory device | Chrong-Jung Lin, Di-Son Kuo | 2002-05-21 |
| 6362035 | Channel stop ion implantation method for CMOS integrated circuits | Jiaw-Ren Shih, Jian-Hsing Lee, Hsien-Chin Lin | 2002-03-26 |
| 6326662 | Split gate flash memory device with source line | Chia-Ta Hsieh, Chrong-Jung Lin, Di-Son Kuo | 2001-12-04 |
| 6323523 | N-type structure for n-type pull-up and down I/O protection circuit | Jian-Hsing Lee, Yi-Hsun Wu, Jiaw-Ren Shih | 2001-11-27 |
| 6306695 | Modified source side inserted anti-type diffusion ESD protection device | Jian-Hsing Lee, Jiaw-Ren Shih, Yi-Hsun Wu | 2001-10-23 |
| 6277723 | Plasma damage protection cell using floating N/P/N and P/N/P structure | Jiaw-Ren Shih, Jian-Hsing Lee, Chrong-Jung Lin | 2001-08-21 |
| 6242314 | Method for fabricating a on-chip temperature controller by co-implant polysilicon resistor | Chrong-Jung Lin, Jiaw-Ren Shih | 2001-06-05 |
| 6232160 | Method of delta-channel in deep sub-micron process | Jiaw-Ren Shih, Jian-Hsing Lee | 2001-05-15 |
| 6225162 | Step-shaped floating poly-si gate to improve gate coupling ratio for flash memory application | Chrong-Jung Lin | 2001-05-01 |
| 6214670 | Method for manufacturing short-channel, metal-gate CMOS devices with superior hot carrier performance | Jiaw-Ren Shih, Jian-Hsing Lee | 2001-04-10 |
| 6207532 | STI process for improving isolation for deep sub-micron application | Chrong-Jung Lin, Jiaw-Ren Shih | 2001-03-27 |
| 6207482 | Integration method for deep sub-micron dual gate transistor design | Jiaw-Ren Shih, Jian-Hsing Lee, Chia-Hung Tunga | 2001-03-27 |
| 6190954 | Robust latchup-immune CMOS structure | Jian-Hsing Lee, Jiaw-Ren Shih | 2001-02-20 |
| 6133097 | Method for forming mirror image split gate flash memory devices by forming a central source line slot | Chia-Ta Hsieh, Chrong-Jung Lin, Di-Son Kuo | 2000-10-17 |
| 6127226 | Method for forming vertical channel flash memory cell using P/N junction isolation | Chrong-Jung Lin, Jong Chen, Di-Son Kuo | 2000-10-03 |
| 6122201 | Clipped sine wave channel erase method to reduce oxide trapping charge generation rate of flash EEPROM | Jian-Hsing Lee, Kuo-Reay Peng, Jiaw-Ren Shih | 2000-09-19 |
| 6093606 | Method of manufacture of vertical stacked gate flash memory device | Chrong-Jung Lin, Mong-Song Liang | 2000-07-25 |
| 6087222 | Method of manufacture of vertical split gate flash memory device | Chrong Jung Lin, Di-Son Kuo | 2000-07-11 |
| 6066874 | Flash memory cell with vertical channels, and source/drain bus lines | Chrong-Jung Lin, Jong Chen, Di-Son Kuo | 2000-05-23 |
| 6033963 | Method of forming a metal gate for CMOS devices using a replacement gate process | Jenn Ming Huang, Chi-Wen Su, Chung-Cheng Wu | 2000-03-07 |
| 6011288 | Flash memory cell with vertical channels, and source/drain bus lines | Chrong-Jung Lin, Jong Chen, Di-Son Kuo | 2000-01-04 |
| 5960284 | Method for forming vertical channel flash memory cell and device manufactured thereby | Chrong-Jung Lin, Jong Chen, Di-Son Kuo | 1999-09-28 |