Issued Patents All Time
Showing 1–25 of 25 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6724036 | Stacked-gate flash memory cell with folding gate and increased coupling ratio | Chia-Ta Hsieh, Di-Son Kuo, Yai-Fen Lin, Chrong-Jung Lin, Hung-Der Su | 2004-04-20 |
| 6495880 | Method to fabricate a flash memory cell with a planar stacked gate | Chrong-Jung Lin, Hung-Der Su, Di-Son Kuo | 2002-12-17 |
| 6437397 | Flash memory cell with vertically oriented channel | Chrong-Jung Lin, Shui-Hung Chen, Di-Son Kuo | 2002-08-20 |
| 6348382 | Integration process to increase high voltage breakdown performance | Hung-Der Su, Chrong-Jung Lin, Wen-Ting Chu | 2002-02-19 |
| 6297098 | Tilt-angle ion implant to improve junction breakdown in flash memory application | Chrong-Jung Lin, Hung-Der Su, Wen-Ting Chu | 2001-10-02 |
| 6261905 | Flash memory structure with stacking gate formed using damascene-like structure | Chrong-Jong Lin, Hung-Der Su, Wen-Ting Chu | 2001-07-17 |
| 6251744 | Implant method to improve characteristics of high voltage isolation and high voltage breakdown | Hung-Der Su, Chrong-Jung Lin, Wen-Ting Chu, Hung-Cheng Sung, Di-Son Kuo | 2001-06-26 |
| 6190969 | Method to fabricate a flash memory cell with a planar stacked gate | Chrong-Jung Lin, Hung-Der Su, Di-Son Kuo | 2001-02-20 |
| 6172395 | Method of manufacture of self-aligned floating gate, flash memory cell and device manufactured thereby | Chrong-Jung Lin | 2001-01-09 |
| 6153494 | Method to increase the coupling ratio of word line to floating gate by lateral coupling in stacked-gate flash | Chia-Ta Hsieh, Di-Son Kuo, Yai-Fen Lin, Chrong-Jung Lin, Hung-Der Su | 2000-11-28 |
| 6133096 | Process for simultaneously fabricating a stack gate flash memory cell and salicided periphereral devices | Hung-Der Su, Chrong-Jung Lin, Di-Son Kuo | 2000-10-17 |
| 6130168 | Using ONO as hard mask to reduce STI oxide loss on low voltage device in flash or EPROM process | Wen-Ting Chu, Di-Son Kuo, Chrong-Jung Lin, Hung-Der Su | 2000-10-10 |
| 6127226 | Method for forming vertical channel flash memory cell using P/N junction isolation | Chrong-Jung Lin, Shui-Hung Chen, Di-Son Kuo | 2000-10-03 |
| 6127227 | Thin ONO thickness control and gradual gate oxidation suppression by b. N.su2 treatment in flash memory | Chrong-Jung Lin, Hung-Der Su, Di-Son Kuo | 2000-10-03 |
| 6124177 | Method for making deep sub-micron mosfet structures having improved electrical characteristics | Chrong-Jung Lin, Hung-Der Su, Wen-Ting Chu | 2000-09-26 |
| 6078076 | Vertical channels in split-gate flash memory cell | Chrong-Jung Lin, Chia-Ta Hsieh, Di-Son Kuo | 2000-06-20 |
| 6074915 | Method of making embedded flash memory with salicide and sac structure | Chrong-Jung Lin, Hung-Der Su, Di-Son Kuo | 2000-06-13 |
| 6066874 | Flash memory cell with vertical channels, and source/drain bus lines | Chrong-Jung Lin, Shui-Hung Chen, Di-Son Kuo | 2000-05-23 |
| 6063664 | Method of making EEPROM with trenched structure | Chrong-Jung Lin, Di-Son Kuo | 2000-05-16 |
| 6037223 | Stack gate flash memory cell featuring symmetric self aligned contact structures | Hung-Der Su, Chrong-Jung Lin, Di-Son Kuo | 2000-03-14 |
| 6013551 | Method of manufacture of self-aligned floating gate, flash memory cell and device manufactured thereby | Chrong-Jung Lin | 2000-01-11 |
| 6011288 | Flash memory cell with vertical channels, and source/drain bus lines | Chrong-Jung Lin, Shui-Hung Chen, Di-Son Kuo | 2000-01-04 |
| 6001687 | Process for forming self-aligned source in flash cell using SiN spacer as hard mask | Wen-Ting Chu, Di-Son Kuo, Chrong-Jung Lin, Hung-Der Su | 1999-12-14 |
| 5970341 | Method for forming vertical channels in split-gate flash memory cell | Chrong-Jung Lin, Chia-Ta Hsieh, Di-Son Kuo | 1999-10-19 |
| 5960284 | Method for forming vertical channel flash memory cell and device manufactured thereby | Chrong-Jung Lin, Shui-Hung Chen, Di-Son Kuo | 1999-09-28 |