Issued Patents All Time
Showing 1–25 of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| RE43426 | Fabrication method of transparent electrode on visible light-emitting diode | Shi-Ming Chen | 2012-05-29 |
| 7541205 | Fabrication method of transparent electrode on visible light-emitting diode | Shi-Ming Chen | 2009-06-02 |
| 7192794 | Fabrication method of transparent electrode on visible light-emitting diode | Shi-Ming Chen | 2007-03-20 |
| 6436762 | Method for improving bit line to capacitor electrical failures on DRAM circuits using a wet etch-back to improve the bit-line-to-capacitor overlay margins | Kuo-Chyuan Tzeng, Min-Hsiung Chiang, Hsiao-Hui Tseng, Chung-Wei Chang | 2002-08-20 |
| 6433665 | High efficiency thin film inductor | Kuo-Ching Huang, Jin-Yuan Lee | 2002-08-13 |
| 6373369 | High efficiency thin film inductor | Kuo-Ching Huang, Jin-Yuan Lee | 2002-04-16 |
| 6306767 | Self-aligned etching method for forming high areal density patterned microelectronic structures | Kuo-Chyuan Tzeng, Wen-Chuan Chiang, Ming-Hsiang Chiang | 2001-10-23 |
| 6307213 | Method for making a fuse structure for improved repaired yields on semiconductor memory devices | Kuo-Ching Huang, Cheng-Yeh Shih, Yu-Hua Lee, Cheng-Ming Wu | 2001-10-23 |
| 6287939 | Method for fabricating a shallow trench isolation which is not susceptible to buried contact trench formation | Kuo-Ching Huang, Wen-Chuan Chiang | 2001-09-11 |
| 6278352 | High efficiency thin film inductor | Kuo-Ching Huang, Jin-Yuan Lee | 2001-08-21 |
| 6214715 | Method for fabricating a self aligned contact which eliminates the key hole problem using a two step spacer deposition | Kuo-Ching Huang, Wen-Chuan Chiang | 2001-04-10 |
| 6207492 | Common gate and salicide word line process for low cost embedded DRAM devices | Kuo-Chyuan Tzeng, Chen-Jong Wang, Kevin Chiang | 2001-03-27 |
| 6194234 | Method to evaluate hemisperical grain (HSG) polysilicon surface | Kuo-Ching Huang, Wen-Chuan Chiang, Yu-Hua Lee | 2001-02-27 |
| 6187659 | Node process integration technology to improve data retention for logic based embedded dram | Wen-Chuan Chiang, Cheng-Ming Wu, Yu-Hua Lee | 2001-02-13 |
| 6174802 | Method for fabricating a self aligned contact which eliminates the key hole problem using a two step contact deposition | Kuo-Ching Huang, Wen-Chuan Chiang, Min-Hsiung Chiang | 2001-01-16 |
| 6168984 | Reduction of the aspect ratio of deep contact holes for embedded DRAM devices | Chue-San Yoo, Ming-Hsiung Chiang, Wen-Chuan Chiang, Cheng-Ming Wu | 2001-01-02 |
| 6162686 | Method for forming a fuse in integrated circuit application | Kuo-Ching Huang, Yu-Hua Lee, Ming Li | 2000-12-19 |
| 6121073 | Method for making a fuse structure for improved repaired yields on semiconductor memory devices | Kuo-Ching Huang, Cheng-Yeh Shih, Yu-Hua Lee, Cheng-Ming Wu | 2000-09-19 |
| 6093619 | Method to form trench-free buried contact in process with STI technology | Kuo-Ching Huang, Chia-Shiung Tsai | 2000-07-25 |
| 6080637 | Shallow trench isolation technology to eliminate a kink effect | Kuo-Ching Huang, Wen-Chuan Chiang, Cheng-Yeh Shih | 2000-06-27 |
| 6037222 | Method for fabricating a dual-gate dielectric module for memory embedded logic using salicide technology and polycide technology | Kuo-Ching Huang, Chen-Jong Wang, Jenn Ming Huang | 2000-03-14 |
| 5946596 | Method for preventing polycide line deformation by polycide hardening | — | 1999-08-31 |
| 5922515 | Approaches to integrate the deep contact module | Wen-Chuan Chiang | 1999-07-13 |
| 5885865 | Method for making low-topography buried capacitor by a two stage etching process and device made | Mong-Song Liang, Julie Huang, Chen-Jong Wang | 1999-03-23 |
| 5811331 | Formation of a stacked cylindrical capacitor module in the DRAM technology | Mong-Song Liang | 1998-09-22 |