Issued Patents All Time
Showing 1–25 of 32 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9899263 | Method of forming layout design | Tung-Heng Hsieh, Chung-Te Lin, Sheng-Hsiung Wang, Hui-Zhong Zhuang, Ting-Wei Chiang +1 more | 2018-02-20 |
| 9691721 | Jog design in integrated circuits | Tsung-Lin Wu, Tung-Heng Hsieh, Jiun-Ming Kuo, Che-Yuan Hsu | 2017-06-27 |
| 9570584 | Semiconductor structure and manufacturing method thereof | Chih-Hsiung Lin, Chia-Der Chang, Pin-Cheng Hsu, Shu-Wei Chung, Hao-Wen Hsu | 2017-02-14 |
| 9355912 | Jog design in integrated circuits | Tsung-Lin Wu, Tung-Heng Hsieh, Jiun-Ming Kuo, Che-Yuan Hsu | 2016-05-31 |
| 9336348 | Method of forming layout design | Tung-Heng Hsieh, Chung-Te Lin, Sheng-Hsiung Wang, Hui-Zhong Zhuang, Ting-Wei Chiang +1 more | 2016-05-10 |
| 8901627 | Jog design in integrated circuits | Tsung-Lin Wu, Tung-Heng Hsieh, Jiun-Ming Kuo, Che-Yuan Che | 2014-12-02 |
| 7622347 | Self-aligned metal electrode to eliminate native oxide effect for metal insulator semiconductor (MIS) capacitor | Chih-Ta Wu, Tsung-Hsun Huang | 2009-11-24 |
| 7332394 | Method to reduce a capacitor depletion phenomena | — | 2008-02-19 |
| 7238566 | Method of forming one-transistor memory cell and structure formed thereby | — | 2007-07-03 |
| 7208369 | Dual poly layer and method of manufacture | Chih-Yang Pai, Chen-Jong Wang, Shou-Gwo Wuu | 2007-04-24 |
| 7180116 | Self-aligned metal electrode to eliminate native oxide effect for metal insulator semiconductor (MIS) capacitor | Chih-Ta Wu, Tsung-Hsun Huang | 2007-02-20 |
| 6849387 | Method for integrating copper process and MIM capacitor for embedded DRAM | Chi-Hsin Lo | 2005-02-01 |
| 6818495 | Method for forming high purity silicon oxide field oxide isolation region | Jin-Yuan Lee, Jenn Ming Huang | 2004-11-16 |
| 6808980 | Method of process simplification and eliminating topography concerns for the creation of advanced 1T-RAM devices | Chung-Yi Chen, Hsien-Yuan Chang | 2004-10-26 |
| 6797557 | Methods and systems for forming embedded DRAM for an MIM capacitor | — | 2004-09-28 |
| 6656786 | MIM process for logic-based embedded RAM having front end manufacturing operation | Hsiao-Hui Tseng, Hsien-Yuan Chang, Tazy-Schiuan Yang | 2003-12-02 |
| 6656785 | MIM process for logic-based embedded RAM | Hsiao-Hui Tseng, Hsien-Yuan Chang | 2003-12-02 |
| 6600228 | Keyhole at the top metal level prefilled with photoresist to prevent passivation damage even for a severe top metal rule | Yu-Hua Lee, Jenn Ming Huang | 2003-07-29 |
| 6569732 | Integrated process sequence allowing elimination of polysilicon residue and silicon damage during the fabrication of a buried stack capacitor structure in a SRAM cell | Chung-Wei Chang, Kuo-Chyuan Tzeng | 2003-05-27 |
| 6495425 | Memory cell structure integrating self aligned contact structure with salicide gate electrode structure | — | 2002-12-17 |
| 6436762 | Method for improving bit line to capacitor electrical failures on DRAM circuits using a wet etch-back to improve the bit-line-to-capacitor overlay margins | Kuo-Chyuan Tzeng, Tse-Liang Ying, Hsiao-Hui Tseng, Chung-Wei Chang | 2002-08-20 |
| 6383863 | Approach to integrate salicide gate for embedded DRAM devices | Hsiao-Hui Tseng, Hsien-Yuan Chang, Chung-Wei Chang, Kuo-Chyuan Tzeng | 2002-05-07 |
| 6365325 | Aperture width reduction method for forming a patterned photoresist layer | Huan-Just Lin, James C. Wu, Cheng-Tung Lin | 2002-04-02 |
| 6294456 | Method of prefilling of keyhole at the top metal level with photoresist to prevent passivation damage even for a severe top metal rule | Yu-Hua Lee, Jenn Ming Huang | 2001-09-25 |
| 6274426 | Self-aligned contact process for a crown shaped dynamic random access memory capacitor structure | Yu-Hua Lee, James Wu | 2001-08-14 |