Issued Patents All Time
Showing 1–14 of 14 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12094872 | Capacitor in nanosheet | Chung-Hui Chen, Wan-Te Chen, Tung-Heng Hsieh, Tzu-Ching Chang, Tsung-Hsin Yu +1 more | 2024-09-17 |
| 12087715 | Integrated circuit features with obtuse angles and method of forming same | Yen-Sen Wang | 2024-09-10 |
| 12073165 | Standard cell design | Tung-Heng Hsieh, Chung-Hui Chen, Chung-Yi Lin | 2024-08-27 |
| 11967550 | Semiconductor structure with via extending across adjacent conductive lines and method of forming the same | Yen-Sen Wang | 2024-04-23 |
| 11503711 | Method for inserting dummy capacitor structures | Yen-Sen Wang | 2022-11-15 |
| 11495558 | Integrated circuit features with obtuse angles and method of forming same | Yen-Sen Wang | 2022-11-08 |
| 10861807 | Integrated circuit features with obtuse angles and method forming same | Yen-Sen Wang | 2020-12-08 |
| 9570584 | Semiconductor structure and manufacturing method thereof | Chih-Hsiung Lin, Chia-Der Chang, Pin-Cheng Hsu, Min-Hsiung Chiang, Hao-Wen Hsu | 2017-02-14 |
| 8951872 | High voltage device with reduced leakage | Kuo-Feng Yu | 2015-02-10 |
| 8664719 | High voltage device with reduced leakage | Kuo-Feng Yu | 2014-03-04 |
| 8450808 | HVMOS devices and methods for forming the same | Kuo-Feng Yu | 2013-05-28 |
| 8373219 | Method of fabricating a gate stack integration of complementary MOS device | Kuo-Feng Yu, Shyue-Shyh Lin | 2013-02-12 |
| 8350327 | High voltage device with reduced leakage | Kuo-Feng Yu | 2013-01-08 |
| 8173499 | Method of fabricating a gate stack integration of complementary MOS device | Kuo-Feng Yu, Shyue-Shyh Lin | 2012-05-08 |