Issued Patents All Time
Showing 1–22 of 22 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12393759 | Integrated circuit layouts with fill feature shapes | Yu-Cheng Yeh, Ming-Yi Lin | 2025-08-19 |
| 12087715 | Integrated circuit features with obtuse angles and method of forming same | Shu-Wei Chung | 2024-09-10 |
| 11967550 | Semiconductor structure with via extending across adjacent conductive lines and method of forming the same | Shu-Wei Chung | 2024-04-23 |
| 11929288 | Gate-all-around device with different channel semiconductor materials and method of forming the same | Jhe-Ching Lu, Bao-Ru Young, Tsung-Chieh Tsai | 2024-03-12 |
| 11894263 | Local interconnect | Cheng-Hsien Wu, Chung-Yi Lin | 2024-02-06 |
| 11735579 | Electrostatic discharge prevention | Ting-Yun Wu, Chung-Yi Lin | 2023-08-22 |
| 11688654 | Test line structure, semiconductor structure and method for forming test line structure | Yen-Chun Lin, Chung-Yi Lin, Bao-Ru Young | 2023-06-27 |
| 11508631 | Semiconductor device | Yen-Chun Lin, Bao-Ru Young, Ting-Yun Wu, Hsiao-Wen Hsu | 2022-11-22 |
| 11508624 | Gate-all-around device with different channel semiconductor materials and method of forming the same | Jhe-Ching Lu, Bao-Ru Young, Tsung-Chieh Tsai | 2022-11-22 |
| 11503711 | Method for inserting dummy capacitor structures | Shu-Wei Chung | 2022-11-15 |
| 11495558 | Integrated circuit features with obtuse angles and method of forming same | Shu-Wei Chung | 2022-11-08 |
| 11334703 | Integrated circuit layouts with fill feature shapes | Yu-Cheng Yeh, Ming-Yi Lin | 2022-05-17 |
| 11036911 | Charging prevention method and structure | Han-Chung Lin, Chung-Yi Lin | 2021-06-15 |
| 10861807 | Integrated circuit features with obtuse angles and method forming same | Shu-Wei Chung | 2020-12-08 |
| 9620420 | Semiconductor arrangement and formation thereof | Chen-Hung Lu, Chie-luan Lin, Ming-Yi Lin, Jyh-Kang Ting | 2017-04-11 |
| 9551923 | Cut mask design layers to provide compact cell height | Ming-Yi Lin, Chen-Hung Lu, Jyh-Kang Ting | 2017-01-24 |
| 9405879 | Cell boundary layout | Ting Yu Chen, Ken-Hsien Hsieh, Ming-Yi Lin, Chen-Hung Lu | 2016-08-02 |
| 9349634 | Semiconductor arrangement and formation thereof | Chen-Hung Lu, Chie-Iuan Lin, Ming-Yi Lin, Jyh-Kang Ting | 2016-05-24 |
| 8389316 | Strain bars in stressed layers of MOS devices | Chung-Te Lin, Min Cao, Sheng-Jier Yang | 2013-03-05 |
| 8227869 | Performance-aware logic operations for generating masks | Lee-Chung Lu, Chung-Te Lin, Yao-Jen Chuang, Gwan Sin Chang | 2012-07-24 |
| 8122394 | Performance-aware logic operations for generating masks | Lee-Chung Lu, Chung-Te Lin, Yao-Jen Chuang, Gwan Sin Chang | 2012-02-21 |
| 7943961 | Strain bars in stressed layers of MOS devices | Chung-Te Lin, Min Cao, Sheng-Jier Yang | 2011-05-17 |