Issued Patents All Time
Showing 1–25 of 26 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11281835 | Cell layout and structure | Tung-Heng Hsieh, Sheng-Hsiung Wang, Hui-Zhong Zhuang, Yu-Cheng Yeh, Tsung-Chieh Tsai +2 more | 2022-03-22 |
| 10998304 | Conductive line patterning | Ru-Gun Liu, Tung-Heng Hsieh, Tsung-Chieh Tsai, Juing-Yi Wu, Liang-Yao Lee | 2021-05-04 |
| 10664639 | Cell layout and structure | Tung-Heng Hsieh, Sheng-Hsiung Wang, Hui-Zhong Zhuang, Yu-Cheng Yeh, Tsung-Chieh Tsai +2 more | 2020-05-26 |
| 10283495 | Mask optimization for multi-layer contacts | Ru-Gun Liu, Chun-Yi Lee, Juing-Yi Wu, Liang-Yao Lee, Tung-Heng Hsieh +1 more | 2019-05-07 |
| 10269785 | Conductive line patterning | Ru-Gun Liu, Tung-Heng Hsieh, Tsung-Chieh Tsai, Juing-Yi Wu, Liang-Yao Lee | 2019-04-23 |
| 9984191 | Cell layout and structure | Tung-Heng Hsieh, Sheng-Hsiung Wang, Hui-Zhong Zhuang, Yu-Cheng Yeh, Tsung-Chieh Tsai +2 more | 2018-05-29 |
| 9746783 | Method for preventing photoresist corner rounding effects | Liang-Yao Lee, Tsung-Chieh Tsai, Juing-Yi Wu | 2017-08-29 |
| 9637818 | Implant region definition | Juing-Yi Wu, Tsung-Chieh Tsai, Liang-Yao Lee | 2017-05-02 |
| 9620420 | Semiconductor arrangement and formation thereof | Chen-Hung Lu, Chie-luan Lin, Ming-Yi Lin, Yen-Sen Wang | 2017-04-11 |
| 9551923 | Cut mask design layers to provide compact cell height | Yen-Sen Wang, Ming-Yi Lin, Chen-Hung Lu | 2017-01-24 |
| 9508791 | Semiconductor device having a metal gate | Tsung-Chieh Tsai, Yung-Che Albert Shih, Juing-Yi Wu, Liang-Yao Lee | 2016-11-29 |
| 9472501 | Conductive line patterning | Ru-Gun Liu, Tung-Heng Hsieh, Tsung-Chieh Tsai, Juing-Yi Wu, Liang-Yao Lee | 2016-10-18 |
| 9391056 | Mask optimization for multi-layer contacts | Ru-Gun Liu, Tung-Heng Hsieh, Tsung-Chieh Tsai, Juing-Yi Wu, Liang-Yao Lee +1 more | 2016-07-12 |
| 9349634 | Semiconductor arrangement and formation thereof | Chen-Hung Lu, Chie-Iuan Lin, Yen-Sen Wang, Ming-Yi Lin | 2016-05-24 |
| 9136168 | Conductive line patterning | Ru-Gun Liu, Tung-Heng Hsieh, Tsung-Chieh Tsai, Juing-Yi Wu, Liang-Yao Lee | 2015-09-15 |
| 9087773 | Implant region definition | Juing-Yi Wu, Tsung-Chieh Tsai, Liang-Yao Lee | 2015-07-21 |
| 9047437 | Method, system and software for accessing design rules and library of design features while designing semiconductor device layout | Chin-An Chen, Pei-Tzu Wu, Tsung-Chieh Tsai, Juing-Yi Wu | 2015-06-02 |
| 8806417 | Rule coverage rate auto-extraction and rule number auto-mark | Chih-Ming Chao, Chin-An Chen, Pei-Tzu Wu, Chun-Yi Lee | 2014-08-12 |
| 8769475 | Method, system and software for accessing design rules and library of design features while designing semiconductor device layout | Chin-An Chen, Pei-Tzu Wu, Tsung-Chieh Tsai, Juing-Yi Wu | 2014-07-01 |
| 6169314 | Layout pattern for improved MOS device matching | Shyh-Chyi Wong, Pin-Nan Tseng | 2001-01-02 |
| 5952698 | Layout pattern for improved MOS device matching | Shyh-Chyi Wong, Pin-Nan Tseng | 1999-09-14 |
| 5838032 | Precision capacitor array | — | 1998-11-17 |
| 5804488 | Method of forming a tungsten silicide capacitor having a high breakdown voltage | Chun-Yi Shih, Shun-Liang Hsu | 1998-09-08 |
| 5635421 | Method of making a precision capacitor array | — | 1997-06-03 |
| 5554558 | Method of making high precision w-polycide-to-poly capacitors in digital/analog process | Shun-Liang Hsu, Chun-Yi Shih | 1996-09-10 |