Issued Patents All Time
Showing 1–25 of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8497584 | Method to improve bump reliability for flip chip device | Yen-Ming Chen, Chia-Fu Lin, Kai-Ming Ching, Hsin-Hui Lee, Chao-Yuan Su +1 more | 2013-07-30 |
| 8389341 | Lateral power MOSFET with high breakdown voltage and low on-resistance | Tsung-Yi Huang, Puo-Yu Chiang, Ruey-Hsin Liu, Chyi-Chyuan Huang, Fu-Hsin Chen +1 more | 2013-03-05 |
| 8129783 | Lateral power MOSFET with high breakdown voltage and low on-resistance | Tsung-Yi Huang, Puo-Yu Chiang, Ruey-Hsin Liu | 2012-03-06 |
| 8114745 | High voltage CMOS devices | Chen-Bau Wu, Chien-Shao Tang, Robin Hsieh, Ruey-Hsin Liu | 2012-02-14 |
| 7989890 | Lateral power MOSFET with high breakdown voltage and low on-resistance | Tsung-Yi Huang, Puo-Yu Chiang, Ruey-Hsin Liu, Chyi-Chyuan Huang, Fu-Hsin Chen +1 more | 2011-08-02 |
| 7911022 | Isolation structure in field device | You-Kuo Wu, An-Min Chiang | 2011-03-22 |
| 7719064 | High voltage CMOS devices | Chen-Bau Wu, Chien-Shao Tang, Robin Hsieh, Ruey-Hsin Liu | 2010-05-18 |
| 7714414 | Method and apparatus for polymer dielectric surface recovery by ion implantation | Hsiu-Mei Yu, Ken-Shen Chou | 2010-05-11 |
| 7521741 | Shielding structures for preventing leakages in high voltage MOS devices | Yu-Chang Jong, Ruey-Hsin Liu, Yueh-Chiou Lin, Chi-Hsuen Chang, Te-Yin Hsia | 2009-04-21 |
| 7521342 | Semiconductor structure with high-voltage sustaining capability and fabrication method of the same | Chen-Bau Wu, Fang-Cheng Lui | 2009-04-21 |
| 7482662 | High voltage semiconductor device utilizing a deep trench structure | Chen-Bau Wu, You-Kuo Wu, Yu-Chang Jong | 2009-01-27 |
| 7476591 | Lateral power MOSFET with high breakdown voltage and low on-resistance | Tsung-Yi Huang, Puo-Yu Chiang, Ruey-Hsin Liu | 2009-01-13 |
| 7384836 | Integrated circuit transistor insulating region fabrication method | You-Kuo Wu, Edward Chiang | 2008-06-10 |
| 7372104 | High voltage CMOS devices | Chen-Bau Wu, Chien-Shao Tang, Robin Hsieh, Ruey-Hsin Liu | 2008-05-13 |
| 7279767 | Semiconductor structure with high-voltage sustaining capability and fabrication method of the same | Chen-Bau Wu, Fang-Cheng Lui | 2007-10-09 |
| 7221021 | Method of forming high voltage devices with retrograde well | Kuo-Ming Wu, Chen-Bau Wu, Ruey-Hsin Liu | 2007-05-22 |
| 7129559 | High voltage semiconductor device utilizing a deep trench structure | Chen-Bau Wu, You-Kuo Wu, Yu-Chang Jong | 2006-10-31 |
| 7122876 | Isolation-region configuration for integrated-circuit transistor | You-Kuo Wu, Edward Chiang | 2006-10-17 |
| 7079412 | Programmable MOS device formed by stressing polycrystalline silicon | Chung-Hui Chen, Yean-Kuen Fang | 2006-07-18 |
| 6756294 | Method for improving bump reliability for flip chip devices | Yen-Ming Chen, Chia-Fu Lin, Kai-Ming Ching, Hsin-Hui Lee, Chao-Yuan Su +1 more | 2004-06-29 |
| 6593220 | Elastomer plating mask sealed wafer level package method | Hsiu-Mei Yu, Ken-Shen Chou, Hsiu-Chieh Cheng | 2003-07-15 |
| 6348371 | Method of forming self-aligned twin wells | Chih-Feng Huang, Kuo-Su Huang | 2002-02-19 |
| 6338976 | Method for forming optoelectronic microelectronic fabrication with attenuated bond pad corrosion | Chieh-Chuan Huang, Cheng-Yu Chu | 2002-01-15 |
| 6291306 | Method of improving the voltage coefficient of resistance of high polysilicon resistors | Yung-Lung Hsu, Yean-Kuen Fang, Mao-Hsiung Kuo | 2001-09-18 |
| 6100154 | Using LPCVD silicon nitride cap as a barrier to reduce resistance variations from hydrogen intrusion of high-value polysilicon resistor | Yung-Lung Hsu | 2000-08-08 |