Issued Patents All Time
Showing 26–47 of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 5972777 | Method of forming isolation by nitrogen implant to reduce bird's beak | Chia-Ta Hsieh | 1999-10-26 |
| 5895257 | LOCOS field oxide and field oxide process using silicon nitride spacers | Chaochieh Tsai, Yuan-Chang Huang, Juing-Yi Wu | 1999-04-20 |
| 5872042 | Method for alignment mark regeneration | Syun-Ming Jang, Chang-Song Lin | 1999-02-16 |
| 5866947 | Post tungsten etch bank anneal, to improve aluminum step coverage | Jyh-Haur Wang | 1999-02-02 |
| 5858854 | Method for forming high contrast alignment marks | Chao-Chieh Tsai, Tsu Shih | 1999-01-12 |
| 5804488 | Method of forming a tungsten silicide capacitor having a high breakdown voltage | Chun-Yi Shih, Jyh-Kang Ting | 1998-09-08 |
| 5757045 | CMOS device structure with reduced risk of salicide bridging and reduced resistance via use of a ultra shallow, junction extension, ion implantation | Chaochieh Tsai | 1998-05-26 |
| 5726091 | Method of reducing bird's beak of field oxide using reoxidized nitrided pad oxide layer | Chao-Chieh Tsai | 1998-03-10 |
| 5705320 | Recovery of alignment marks and laser marks after chemical-mechanical-polishing | Shih-Shiung Chen | 1998-01-06 |
| 5702972 | Method of fabricating MOSFET devices | Chaochieh Tsai, Shaulin Shue | 1997-12-30 |
| 5691212 | MOS device structure and integration method | Chaochieh Tsai | 1997-11-25 |
| 5668024 | CMOS device structure with reduced risk of salicide bridging and reduced resistance via use of a ultra shallow, junction extension, ion implantation process | Chaochieh Tsai | 1997-09-16 |
| 5641710 | Post tungsten etch back anneal, to improve aluminum step coverage | Jyh-Haur Wang | 1997-06-24 |
| 5597442 | Chemical/mechanical planarization (CMP) endpoint method using measurement of polishing pad temperature | Hsi-Chieh Chen | 1997-01-28 |
| 5554558 | Method of making high precision w-polycide-to-poly capacitors in digital/analog process | Jyh-Kang Ting, Chun-Yi Shih | 1996-09-10 |
| 5530418 | Method for shielding polysilicon resistors from hydrogen intrusion | Han-Liang Tseng, Mou-Shiung Lin | 1996-06-25 |
| 5510637 | Fabrication of w-polycide-to-poly capacitors with high linearity | Mou-Shiung Lin, Ming Lei | 1996-04-23 |
| 5480828 | Differential gate oxide process by depressing or enhancing oxidation rate for mixed 3/5 V CMOS process | Jyh-Min Tsaur, Mou-Shing Lin, Jyh-Kang Ting | 1996-01-02 |
| 5460993 | Method of making NMOS and PMOS LDD transistors utilizing thinned sidewall spacers | Shyh-Chyi Wong | 1995-10-24 |
| 5451529 | Method of making a real time ion implantation metal silicide monitor | Chun-Yi Shih | 1995-09-19 |
| 5338701 | Method for fabrication of w-polycide-to-poly capacitors with high linearity | Chun-Yi Shi, Mou-Shiung Lin | 1994-08-16 |
| 5108937 | Method of making a recessed gate MOSFET device structure | Yu-Hsein Tsai | 1992-04-28 |