Issued Patents All Time
Showing 1–23 of 23 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| RE41668 | Seal ring structure for radio frequency integrated circuits | Shyh Chih Wong | 2010-09-14 |
| 7265438 | RF seal ring structure | Shyh-Ch Wong | 2007-09-04 |
| 7081648 | Lossless co-planar wave guide in CMOS process | — | 2006-07-25 |
| 7061056 | High fMAX deep submicron MOSFET | Shyh-Chyi Wong, Chung-Long Chang | 2006-06-13 |
| 6967392 | Seal ring structure for radio frequency integrated circuits | Shih Chih Wong | 2005-11-22 |
| 6646328 | Chip antenna with a shielding layer | — | 2003-11-11 |
| 6613623 | High fMAX deep submicron MOSFET | Shyh-Chyi Wong, Chung-Long Chang | 2003-09-02 |
| 6537849 | Seal ring structure for radio frequency integrated circuits | Shih Chih Wong | 2003-03-25 |
| 6521971 | Metal fuse in copper dual damascene | — | 2003-02-18 |
| 6376351 | High Fmax RF MOSFET with embedded stack gate | — | 2002-04-23 |
| 6303448 | Method for fabricating raised source/drain structures | Shou-Zen Chang | 2001-10-16 |
| 6295721 | Metal fuse in copper dual damascene | — | 2001-10-02 |
| 6258688 | Method to form a high Q inductor | — | 2001-07-10 |
| 6245637 | STI process | — | 2001-06-12 |
| 6180445 | Method to fabricate high Q inductor by redistribution layer when flip-chip package is employed | — | 2001-01-30 |
| 6083824 | Borderless contact | Chin-Hsiung Ho, Yuan-Chen Sun | 2000-07-04 |
| 6020255 | Dual damascene interconnect process with borderless contact | Chin-Hsiung Ho, Yuan-Chen Sun | 2000-02-01 |
| 5982017 | Recessed structure for shallow trench isolation and salicide processes | Sheng-Jyh Wu, Jing-Meng Liu | 1999-11-09 |
| 5891771 | Recessed structure for shallow trench isolation and salicide process | Sheng-Jyh Wu, Jing-Meng Liu | 1999-04-06 |
| 5858854 | Method for forming high contrast alignment marks | Shun-Liang Hsu, Tsu Shih | 1999-01-12 |
| 5858846 | Salicide integration method | Wen-Chen Lin, Liang Szuma | 1999-01-12 |
| 5726091 | Method of reducing bird's beak of field oxide using reoxidized nitrided pad oxide layer | Shun-Liang Hsu | 1998-03-10 |
| 5648287 | Method of salicidation for deep quarter micron LDD MOSFET devices | Shie-Sen Peng | 1997-07-15 |