Issued Patents All Time
Showing 1–11 of 11 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6716740 | Method for depositing silicon oxide incorporating an outgassing step | Shih-Ming Wang, Long-Shang Chuang, Jui-Ping Chuang, Mei-Yen Li, Chien-Kang Chou | 2004-04-06 |
| 6647998 | Electrostatic charge-free solvent-type dryer for semiconductor wafers | Jih-Churng Twu, Ming-Dar Guo, Tsung-Chieh Tsai, Sheng-Hsiung Tseng, Wei-Ming You +3 more | 2003-11-18 |
| 6555477 | Method for preventing Cu CMP corrosion | Chen-Fa Lu, Mei-Ling Chen, Liang-Kun Huang | 2003-04-29 |
| 6207538 | Method for forming n and p wells in a semiconductor substrate using a single masking step | Kuo-Hua Pan, Chu-Wei Hu, Chung-Te Lin | 2001-03-27 |
| 6103581 | Method for producing shallow trench isolation structure | Chung-Te Lin, Hann-Huei Tsai | 2000-08-15 |
| 6083824 | Borderless contact | Chao-Chieh Tsai, Yuan-Chen Sun | 2000-07-04 |
| 6063695 | Simplified process for the fabrication of deep clear laser marks using a photoresist mask | Chung-Te Lin, Hsueh-Liang Chiu, So Wein Kuo | 2000-05-16 |
| 6037204 | Silicon and arsenic double implanted pre-amorphization process for salicide technology | Shou-Zen Chang, Chaochieh Tsai, Cheng-Kun Lin | 2000-03-14 |
| 6020255 | Dual damascene interconnect process with borderless contact | Chao-Chieh Tsai, Yuan-Chen Sun | 2000-02-01 |
| 5821153 | Method to reduce field oxide loss from etches | Chaochieh Tsai | 1998-10-13 |
| 5674775 | Isolation trench with a rounded top edge using an etch buffer layer | Chia-Shiung Tsai, Cheng-Kai Liu, Chaochieh Tsai | 1997-10-07 |