Issued Patents All Time
Showing 1–25 of 63 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8890336 | Cylindrical bonding structure and method of manufacture | Jin-Yuan Lee, Shih-Hsiung Lin, Hsi-Shan Kuo | 2014-11-18 |
| 8884433 | Circuitry component and method for forming the same | Mou-Shiung Lin, Ke-Hung Chen | 2014-11-11 |
| 8836146 | Chip package and method for fabricating the same | Chiu-Ming Chou, Li-Ren Lin, Hsin-Jung Lo | 2014-09-16 |
| 8723322 | Method of metal sputtering for integrated circuit metal routing | Hsien-Tsung Liu, Ching-San Lin | 2014-05-13 |
| 8692374 | Carbon nanotube circuit component structure | Mou-Shiung Lin, Hsin-Jung Lo | 2014-04-08 |
| 8674507 | Wafer level processing method and structure to manufacture two kinds of interconnects, gold and solder, on one wafer | Chiu-Ming Chou, Li-Ren Lin, Chu-Fu Lin | 2014-03-18 |
| 8618580 | Integrated circuit chips with fine-line metal and over-passivation metal | Mou-Shiung Lin, Jin-Yuan Lee | 2013-12-31 |
| 8558383 | Post passivation structure for a semiconductor device and packaging process for same | Mou-Shiung Lin, Ke-Hung Chen | 2013-10-15 |
| 8552559 | Very thick metal interconnection scheme in IC chips | Mou-Shiung Lin, Chiu-Ming Chou | 2013-10-08 |
| 8461679 | Method for fabricating circuit component | Jin-Yuan Lee, Shih-Hsiung Lin, Hsi-Shan Kuo | 2013-06-11 |
| 8399989 | Metal pad or metal bump over pad exposed by passivation layer | Mou-Shiung Lin, Hsin-Jung Lo, Chiu-Ming Chou, Ke-Hung Chen | 2013-03-19 |
| 8373202 | Integrated circuit chips with fine-line metal and over-passivation metal | Mou-Shiung Lin, Jin-Yuan Lee | 2013-02-12 |
| 8362588 | Semiconductor chip with coil element over passivation layer | Wen-Chieh Lee, Mou-Shiung Lin, Yi-Cheng Liu, Chiu-Ming Chou, Jin-Yuan Lee | 2013-01-29 |
| 8319354 | Semiconductor chip with post-passivation scheme formed over passivation layer | Mou-Shiung Lin, Hsin-Jung Lo, Chiu-Ming Chou, Ching-San Lin | 2012-11-27 |
| 8304907 | Top layers of metal for integrated circuits | Mou-Shiung Lin, Chiu-Ming Chou | 2012-11-06 |
| 8242601 | Semiconductor chip with passivation layer comprising metal interconnect and contact pads | Chiu-Ming Chou, Ching-San Lin, Mou-Shiung Lin | 2012-08-14 |
| 8198729 | Connection between a semiconductor chip and a circuit component with a large contact area | Chiu-Ming Chou, Mou-Shiung Lin | 2012-06-12 |
| 8187965 | Wirebond pad for semiconductor chip or wafer | Mou-Shiung Lin, Michael Chen, Mark Chou | 2012-05-29 |
| 8159074 | Chip structure | Mou-Shiung Lin, Chiu-Ming Chou, Hsin-Jung Lo | 2012-04-17 |
| 8148822 | Bonding pad on IC substrate and method for making the same | Mou-Shiung Lin, Hsin-Jung Lo, Chiu-Ming Chou, Ke-Hung Chen | 2012-04-03 |
| 8120181 | Post passivation interconnection process and structures | Mou-Shiung Lin, Chiu-Ming Chou | 2012-02-21 |
| 8021918 | Integrated circuit chips with fine-line metal and over-passivation metal | Mou-Shiung Lin, Jin-Yuan Lee | 2011-09-20 |
| 8018060 | Post passivation interconnection process and structures | Mou-Shiung Lin, Chiu-Ming Chou | 2011-09-13 |
| 8013449 | Post passivation interconnection schemes on top of the IC chips | Mou-Shiung Lin, Chiu-Ming Chou | 2011-09-06 |
| 8008775 | Post passivation interconnection structures | Mou-Shiung Lin, Chiu-Ming Chou | 2011-08-30 |