Issued Patents All Time
Showing 1–25 of 31 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12176278 | 3D chip package based on vertical-through-via connector | Ping-Jung Yang, Mou-Shiung Lin, Jin-Yuan Lee, Chiu-Ming Chou | 2024-12-24 |
| 9612615 | Integrated circuit chip using top post-passivation technology and bottom structure technology | Mou-Shiung Lin, Jin-Yuan Lee, Ping-Jung Yang, Te-Sheng Liu | 2017-04-04 |
| 8836146 | Chip package and method for fabricating the same | Chien-Kang Chou, Chiu-Ming Chou, Li-Ren Lin | 2014-09-16 |
| 8837872 | Waveguide structures for signal and/or power transmission in a semiconductor device | Ping-Jung Yang, Te-Sheng Liu | 2014-09-16 |
| 8692374 | Carbon nanotube circuit component structure | Mou-Shiung Lin, Chien-Kang Chou | 2014-04-08 |
| 8456856 | Integrated circuit chip using top post-passivation technology and bottom structure technology | Mou-Shiung Lin, Jin-Yuan Lee, Ping-Jung Yang, Te-Sheng Liu | 2013-06-04 |
| 8426958 | Stacked chip package with redistribution lines | Mou-Shiung Lin, Shih-Hsiung Lin, Ying-Chih Chen, Chiu-Ming Chou | 2013-04-23 |
| 8399989 | Metal pad or metal bump over pad exposed by passivation layer | Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou, Ke-Hung Chen | 2013-03-19 |
| 8368193 | Chip package | Mou-Shiung Lin, Shih-Hsiung Lin | 2013-02-05 |
| 8344524 | Wire bonding method for preventing polymer cracking | Chiu-Ming Chou, Shih-Hsiung Lin, Mou-Shiung Lin | 2013-01-01 |
| 8319354 | Semiconductor chip with post-passivation scheme formed over passivation layer | Mou-Shiung Lin, Chien-Kang Chou, Chiu-Ming Chou, Ching-San Lin | 2012-11-27 |
| 8304766 | Semiconductor chip with a bonding pad having contact and test areas | Mou-Shiung Lin, Huei-Mei Yen, Chiu-Ming Chou, Ke-Hung Chen | 2012-11-06 |
| 8232192 | Process of bonding circuitry components | Mou-Shiung Lin, Shih-Hsiung Lin | 2012-07-31 |
| 8193636 | Chip assembly with interconnection by metal bump | Jin-Yuan Lee | 2012-06-05 |
| 8159074 | Chip structure | Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou | 2012-04-17 |
| 8148822 | Bonding pad on IC substrate and method for making the same | Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou, Ke-Hung Chen | 2012-04-03 |
| 8044475 | Chip package | Mou-Shiung Lin, Shih-Hsiung Lin | 2011-10-25 |
| 8004092 | Semiconductor chip with post-passivation scheme formed over passivation layer | Mou-Shiung Lin, Chien-Kang Chou, Chiu-Ming Chou, Ching-San Lin | 2011-08-23 |
| 7990037 | Carbon nanotube circuit component structure | Mou-Shiung Lin, Chien-Kang Chou | 2011-08-02 |
| 7973401 | Stacked chip package with redistribution lines | Mou-Shiung Lin, Shih-Hsiung Lin, Ying-Chih Chen, Chiu-Ming Chou | 2011-07-05 |
| 7964973 | Chip structure | Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou | 2011-06-21 |
| 7964961 | Chip package | Jin-Yuan Lee | 2011-06-21 |
| 7960269 | Method for forming a double embossing structure | Mou-Shiung Lin, Chiu-Ming Chou, Chien-Kang Chou | 2011-06-14 |
| 7947978 | Semiconductor chip with bond area | Mou-Shiung Lin, Huei-Mei Yen, Chiu-Ming Chou, Ke-Hung Chen | 2011-05-24 |
| 7932172 | Semiconductor chip and process for forming the same | Mou-Shiung Lin, Chien-Kang Chou | 2011-04-26 |