Issued Patents All Time
Showing 1–25 of 53 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12176278 | 3D chip package based on vertical-through-via connector | Ping-Jung Yang, Mou-Shiung Lin, Jin-Yuan Lee, Hsin-Jung Lo | 2024-12-24 |
| 8836146 | Chip package and method for fabricating the same | Chien-Kang Chou, Li-Ren Lin, Hsin-Jung Lo | 2014-09-16 |
| 8674507 | Wafer level processing method and structure to manufacture two kinds of interconnects, gold and solder, on one wafer | Chien-Kang Chou, Li-Ren Lin, Chu-Fu Lin | 2014-03-18 |
| 8592977 | Integrated circuit (IC) chip and method for fabricating the same | Jin-Yuan Lee | 2013-11-26 |
| 8581404 | Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures | Mou-Shiung Lin | 2013-11-12 |
| 8552559 | Very thick metal interconnection scheme in IC chips | Mou-Shiung Lin, Chien-Kang Chou | 2013-10-08 |
| 8519552 | Chip structure | Mou-Shiung Lin | 2013-08-27 |
| 8426958 | Stacked chip package with redistribution lines | Mou-Shiung Lin, Shih-Hsiung Lin, Hsin-Jung Lo, Ying-Chih Chen | 2013-04-23 |
| 8399989 | Metal pad or metal bump over pad exposed by passivation layer | Mou-Shiung Lin, Hsin-Jung Lo, Chien-Kang Chou, Ke-Hung Chen | 2013-03-19 |
| 8362588 | Semiconductor chip with coil element over passivation layer | Wen-Chieh Lee, Mou-Shiung Lin, Chien-Kang Chou, Yi-Cheng Liu, Jin-Yuan Lee | 2013-01-29 |
| 8344524 | Wire bonding method for preventing polymer cracking | Shih-Hsiung Lin, Mou-Shiung Lin, Hsin-Jung Lo | 2013-01-01 |
| 8319354 | Semiconductor chip with post-passivation scheme formed over passivation layer | Mou-Shiung Lin, Hsin-Jung Lo, Chien-Kang Chou, Ching-San Lin | 2012-11-27 |
| 8304907 | Top layers of metal for integrated circuits | Mou-Shiung Lin, Chien-Kang Chou | 2012-11-06 |
| 8304766 | Semiconductor chip with a bonding pad having contact and test areas | Mou-Shiung Lin, Huei-Mei Yen, Hsin-Jung Lo, Ke-Hung Chen | 2012-11-06 |
| 8242601 | Semiconductor chip with passivation layer comprising metal interconnect and contact pads | Chien-Kang Chou, Ching-San Lin, Mou-Shiung Lin | 2012-08-14 |
| 8198729 | Connection between a semiconductor chip and a circuit component with a large contact area | Chien-Kang Chou, Mou-Shiung Lin | 2012-06-12 |
| 8168527 | Semiconductor chip and method for fabricating the same | Mou-Shiung Lin | 2012-05-01 |
| 8159074 | Chip structure | Mou-Shiung Lin, Chien-Kang Chou, Hsin-Jung Lo | 2012-04-17 |
| 8148822 | Bonding pad on IC substrate and method for making the same | Mou-Shiung Lin, Hsin-Jung Lo, Chien-Kang Chou, Ke-Hung Chen | 2012-04-03 |
| 8120181 | Post passivation interconnection process and structures | Mou-Shiung Lin, Chien-Kang Chou | 2012-02-21 |
| 8022544 | Chip structure | Mou-Shiung Lin | 2011-09-20 |
| 8018060 | Post passivation interconnection process and structures | Mou-Shiung Lin, Chien-Kang Chou | 2011-09-13 |
| 8013449 | Post passivation interconnection schemes on top of the IC chips | Mou-Shiung Lin, Chien-Kang Chou | 2011-09-06 |
| 8008775 | Post passivation interconnection structures | Mou-Shiung Lin, Chien-Kang Chou | 2011-08-30 |
| 8004092 | Semiconductor chip with post-passivation scheme formed over passivation layer | Mou-Shiung Lin, Hsin-Jung Lo, Chien-Kang Chou, Ching-San Lin | 2011-08-23 |