Issued Patents All Time
Showing 26–50 of 53 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7985653 | Semiconductor chip with coil element over passivation layer | Wen-Chieh Lee, Mou-Shiung Lin, Chien-Kang Chou, Yi-Cheng Liu, Jin-Yuan Lee | 2011-07-26 |
| 7977803 | Chip structure with bumps and testing pads | Nick Kuo, Chien-Kang Chou, Chu-Fu Lin | 2011-07-12 |
| 7973401 | Stacked chip package with redistribution lines | Mou-Shiung Lin, Shih-Hsiung Lin, Hsin-Jung Lo, Ying-Chih Chen | 2011-07-05 |
| 7964973 | Chip structure | Mou-Shiung Lin, Chien-Kang Chou, Hsin-Jung Lo | 2011-06-21 |
| 7960269 | Method for forming a double embossing structure | Hsin-Jung Lo, Mou-Shiung Lin, Chien-Kang Chou | 2011-06-14 |
| 7947978 | Semiconductor chip with bond area | Mou-Shiung Lin, Huei-Mei Yen, Hsin-Jung Lo, Ke-Hung Chen | 2011-05-24 |
| 7919412 | Over-passivation process of forming polymer layer over IC chip | Ying-Chih Chen, Mou-Shiung Lin | 2011-04-05 |
| 7880304 | Post passivation interconnection schemes on top of the IC chips | Mou-Shiung Lin, Chien-Kang Chou | 2011-02-01 |
| 7855461 | Chip structure with bumps and testing pads | Nick Kuo, Chien-Kang Chou, Chu-Fu Lin | 2010-12-21 |
| 7592205 | Over-passivation process of forming polymer layer over IC chip | Ying-Chih Chen, Mou-Shiung Lin | 2009-09-22 |
| 7582966 | Semiconductor chip and method for fabricating the same | Mou-Shiung Lin | 2009-09-01 |
| 7547969 | Semiconductor chip with passivation layer comprising metal interconnect and contact pads | Chien-Kang Chou, Ching-San Lin, Mou-Shiung Lin | 2009-06-16 |
| 7521805 | Post passivation interconnection schemes on top of the IC chips | Mou-Shiung Lin, Chien-Kang Chou | 2009-04-21 |
| 7508059 | Stacked chip package with redistribution lines | Mou-Shiung Lin, Shih-Hsiung Lin, Hsin-Jung Lo, Ying-Chih Chen | 2009-03-24 |
| 7482268 | Top layers of metal for integrated circuits | Mou-Shiung Lin, Chien-Kang Chou | 2009-01-27 |
| 7470927 | Semiconductor chip with coil element over passivation layer | Wen-Chieh Lee, Mou-Shiung Lin, Chien-Kang Chou, Yi-Cheng Liu, Jin-Yuan Lee | 2008-12-30 |
| 7465654 | Structure of gold bumps and gold conductors on one IC die and methods of manufacturing the structures | Mou-Shiung Lin | 2008-12-16 |
| 7462558 | Method for fabricating a circuit component | Mou-Shiung Lin, Chien-Kang Chou, Hsin-Jung Lo | 2008-12-09 |
| 7452803 | Method for fabricating chip structure | Mou-Shiung Lin, Chien-Kang Chou, Hsin-Jung Lo | 2008-11-18 |
| 7423346 | Post passivation interconnection process and structures | Mou-Shiung Lin, Chien-Kang Chou | 2008-09-09 |
| 7417317 | Post passivation interconnection schemes on top of the IC chips | Mou-Shiung Lin, Chien-Kang Chou | 2008-08-26 |
| 7416971 | Top layers of metal for integrated circuits | Mou-Shiung Lin, Chien-Kang Chou | 2008-08-26 |
| 7397121 | Semiconductor chip with post-passivation scheme formed over passivation layer | Chien-Kang Chou, Ching-San Lin, Mou-Shiung Lin, Hsin-Jung Lo | 2008-07-08 |
| 7394161 | Chip structure with pads having bumps or wirebonded wires formed thereover or used to be tested thereto | Nick Kuo, Chien-Kang Chou, Chu-Fu Lin | 2008-07-01 |
| 7381642 | Top layers of metal for integrated circuits | Mou-Shiung Lin, Chien-Kang Chou | 2008-06-03 |