Issued Patents All Time
Showing 51–63 of 63 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7416971 | Top layers of metal for integrated circuits | Mou-Shiung Lin, Chiu-Ming Chou | 2008-08-26 |
| 7417317 | Post passivation interconnection schemes on top of the IC chips | Mou-Shiung Lin, Chiu-Ming Chou | 2008-08-26 |
| 7397121 | Semiconductor chip with post-passivation scheme formed over passivation layer | Chiu-Ming Chou, Ching-San Lin, Mou-Shiung Lin, Hsin-Jung Lo | 2008-07-08 |
| 7394161 | Chip structure with pads having bumps or wirebonded wires formed thereover or used to be tested thereto | Nick Kuo, Chiu-Ming Chou, Chu-Fu Lin | 2008-07-01 |
| 7381642 | Top layers of metal for integrated circuits | Mou-Shiung Lin, Chiu-Ming Chou | 2008-06-03 |
| 7372161 | Post passivation interconnection schemes on top of the IC chips | Mou-Shiung Lin, Chiu-Ming Chou | 2008-05-13 |
| 7355282 | Post passivation interconnection process and structures | Mou-Shiung Lin, Chiu-Ming Chou | 2008-04-08 |
| 7271489 | Post passivation interconnection schemes on top of the IC chips | Mou-Shiung Lin, Chiu-Ming Chou | 2007-09-18 |
| 7208834 | Bonding structure with pillar and cap | Jin-Yuan Lee, Shih-Hsiung Lin, Hsi-Shan Kuo | 2007-04-24 |
| 6802945 | Method of metal sputtering for integrated circuit metal routing | Hsien-Tsung Liu, Ching-San Lin | 2004-10-12 |
| 6784087 | Method of fabricating cylindrical bonding structure | Jin-Yuan Lee, Shih-Hsiung Lin, Hsi-Shan Kuo | 2004-08-31 |
| 6716740 | Method for depositing silicon oxide incorporating an outgassing step | Shih-Ming Wang, Long-Shang Chuang, Jui-Ping Chuang, Chin-Hsiung Ho, Mei-Yen Li | 2004-04-06 |
| 5580112 | Vacuum pencil having a short tip with an abutment means | Dean E. Lin, Chih-MIing Chen | 1996-12-03 |