Issued Patents All Time
Showing 26–50 of 63 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8004083 | Integrated circuit chips with fine-line metal and over-passivation metal | Mou-Shiung Lin, Jin-Yuan Lee | 2011-08-23 |
| 8004092 | Semiconductor chip with post-passivation scheme formed over passivation layer | Mou-Shiung Lin, Hsin-Jung Lo, Chiu-Ming Chou, Ching-San Lin | 2011-08-23 |
| 7989954 | Integrated circuit chips with fine-line metal and over-passivation metal | Mou-Shiung Lin, Jin-Yuan Lee | 2011-08-02 |
| 7990037 | Carbon nanotube circuit component structure | Mou-Shiung Lin, Hsin-Jung Lo | 2011-08-02 |
| 7985653 | Semiconductor chip with coil element over passivation layer | Wen-Chieh Lee, Mou-Shiung Lin, Yi-Cheng Liu, Chiu-Ming Chou, Jin-Yuan Lee | 2011-07-26 |
| 7977803 | Chip structure with bumps and testing pads | Nick Kuo, Chiu-Ming Chou, Chu-Fu Lin | 2011-07-12 |
| 7969006 | Integrated circuit chips with fine-line metal and over-passivation metal | Mou-Shiung Lin, Jin-Yuan Lee | 2011-06-28 |
| 7964973 | Chip structure | Mou-Shiung Lin, Chiu-Ming Chou, Hsin-Jung Lo | 2011-06-21 |
| 7960270 | Method for fabricating circuit component | Jin-Yuan Lee, Shih-Hsiung Lin, Hsi-Shan Kuo | 2011-06-14 |
| 7960269 | Method for forming a double embossing structure | Hsin-Jung Lo, Mou-Shiung Lin, Chiu-Ming Chou | 2011-06-14 |
| 7932172 | Semiconductor chip and process for forming the same | Mou-Shiung Lin, Hsin-Jung Lo | 2011-04-26 |
| 7880304 | Post passivation interconnection schemes on top of the IC chips | Mou-Shiung Lin, Chiu-Ming Chou | 2011-02-01 |
| 7855461 | Chip structure with bumps and testing pads | Nick Kuo, Chiu-Ming Chou, Chu-Fu Lin | 2010-12-21 |
| 7582556 | Circuitry component and method for forming the same | Mou-Shiung Lin, Ke-Hung Chen | 2009-09-01 |
| 7554208 | Wirebond pad for semiconductor chip or wafer | Mark Chou, Michael Chen, Mou-Shiung Lin | 2009-06-30 |
| 7547969 | Semiconductor chip with passivation layer comprising metal interconnect and contact pads | Chiu-Ming Chou, Ching-San Lin, Mou-Shiung Lin | 2009-06-16 |
| 7521805 | Post passivation interconnection schemes on top of the IC chips | Mou-Shiung Lin, Chiu-Ming Chou | 2009-04-21 |
| 7482268 | Top layers of metal for integrated circuits | Mou-Shiung Lin, Chiu-Ming Chou | 2009-01-27 |
| 7473999 | Semiconductor chip and process for forming the same | Mou-Shiung Lin, Hsin-Jung Lo | 2009-01-06 |
| 7470997 | Wirebond pad for semiconductor chip or wafer | Mou-Shiung Lin, Michael Chen, Mark Chou | 2008-12-30 |
| 7470927 | Semiconductor chip with coil element over passivation layer | Wen-Chieh Lee, Mou-Shiung Lin, Yi-Cheng Liu, Chiu-Ming Chou, Jin-Yuan Lee | 2008-12-30 |
| 7468545 | Post passivation structure for a semiconductor device and packaging process for same | Mou-Shiung Lin, Ke-Hung Chen | 2008-12-23 |
| 7462558 | Method for fabricating a circuit component | Mou-Shiung Lin, Chiu-Ming Chou, Hsin-Jung Lo | 2008-12-09 |
| 7452803 | Method for fabricating chip structure | Mou-Shiung Lin, Chiu-Ming Chou, Hsin-Jung Lo | 2008-11-18 |
| 7423346 | Post passivation interconnection process and structures | Mou-Shiung Lin, Chiu-Ming Chou | 2008-09-09 |