Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11728320 | Semiconductor package | Tien-Yu Lu, Hsin-Hsin Hsiao | 2023-08-15 |
| 11342316 | Semiconductor package | Tien-Yu Lu, Hsin-Hsin Hsiao | 2022-05-24 |
| 10418480 | Semiconductor device capable of high-voltage operation | Cheng-Hua LIN | 2019-09-17 |
| 9793337 | Integrated circuits and fabrication methods thereof | Yuan-Fu CHUNG, Yuan-Hung Chung | 2017-10-17 |
| 9508786 | Integrated circuits and fabrication methods thereof | Yuan-Fu CHUNG, Yuan-Hung Chung | 2016-11-29 |
| 9379175 | Integrated circuits and fabrication methods thereof | Yuan-Fu CHUNG, Yuan-Hung Chung | 2016-06-28 |
| 9123558 | Bipolar junction transistor | Sheng-Hung FAN, Chien-Chih Lin, Chih-Chung Chiu, Zheng Zeng, Wei-Li Tsao | 2015-09-01 |
| 8932937 | Photoresist mask-free oxide define region (ODR) | Chu-Sheng Lee, Hsin-Chi Chen | 2015-01-13 |
| 6951803 | Method to prevent passivation layer peeling in a solder bump formation process | Kai-Meng Tzeng, Cheng-Ming Wu, Jung-Lieh Hsu, Kuei-Yuam Hsu | 2005-10-04 |
| 6790756 | Self aligned channel implant, elevated S/D process by gate electrode damascene | Jiue-Wen Weng, Chung-Te Lin, So Wein Kuo | 2004-09-14 |
| 6787470 | Sacrificial feature for corrosion prevention during CMP | Tsu Shih, Chen Cheng Chou | 2004-09-07 |
| 6583017 | Self aligned channel implant, elevated S/D process by gate electrode damascene | Jiue-Wen Weng, Chung-Te Lin, So Wein Kuo | 2003-06-24 |
| 6451679 | Ion mixing between two-step titanium deposition process for titanium salicide CMOS technology | Jine-Wen Weng, Ruey-Yun Shiue | 2002-09-17 |
| 6444544 | Method of forming an aluminum protection guard structure for a copper metal structure | Chung-Te Lin, Kuo-Hua Pan, Hsien-Chin Lin | 2002-09-03 |
| 6287926 | Self aligned channel implant, elevated S/D process by gate electrode damascene | Jiue-Wen Weng, Chung-Te Lin, So Wein Kuo | 2001-09-11 |
| 6211069 | Dual damascene process flow for a deep sub-micron technology | Jiue-Wen Weng, Ruey-Yun Shiue | 2001-04-03 |
| 6207538 | Method for forming n and p wells in a semiconductor substrate using a single masking step | Kuo-Hua Pan, Chung-Te Lin, Chin-Hsiung Ho | 2001-03-27 |
| 6169003 | Method for forming a MOS device with an elevated source and drain, and having a self-aligned channel input | Jine-Wen Weng | 2001-01-02 |
| 6074905 | Formation of a thin oxide protection layer at poly sidewall and area surface | Chung-Te Lin, Chin-Shan Hou, Kuo-Hua Pan | 2000-06-13 |