Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6790756 | Self aligned channel implant, elevated S/D process by gate electrode damascene | Chu-Wei Hu, Chung-Te Lin, So Wein Kuo | 2004-09-14 |
| 6583017 | Self aligned channel implant, elevated S/D process by gate electrode damascene | Chu-Wei Hu, Chung-Te Lin, So Wein Kuo | 2003-06-24 |
| 6287926 | Self aligned channel implant, elevated S/D process by gate electrode damascene | Chu-Wei Hu, Chung-Te Lin, So Wein Kuo | 2001-09-11 |
| 6211069 | Dual damascene process flow for a deep sub-micron technology | Chu-Wei Hu, Ruey-Yun Shiue | 2001-04-03 |
| 6140693 | Method for making metal capacitors for deep submicrometer processes for semiconductor integrated circuits | Ruey-Yun Shiue | 2000-10-31 |
| 5946567 | Method for making metal capacitors for deep submicrometer processes for semiconductor integrated circuits | Ruey-Yun Shiue | 1999-08-31 |
| 5631188 | Low voltage coefficient polysilicon capacitor | Ming-Hsung Chang | 1997-05-20 |