Issued Patents All Time
Showing 1–10 of 10 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7464357 | Integrated circuit capable of locating failure process layers | An-Ru Cheng, Tzu-Chun Liu, Huan-Yung Tseng | 2008-12-09 |
| 7036099 | Integrated circuit capable of locating failure process layers | An-Ru Cheng, Tzu-Chun Liu, Huan-Yung Tseng | 2006-04-25 |
| 6753569 | Method to fabricate a non-smiling effect structure in split-gate flash with self-aligned isolation | Yai-Fen Lin, Chia-Ta Hsieh, Hung-Cheng Sung, Juang-Ke Yeh | 2004-06-22 |
| 6417046 | Modified nitride spacer for solving charge retention issue in floating gate memory cell | Ming-Chou Ho, Wen-Ting Chu, Chuan-Li Chang, Hsin-Ming Chen, Di-Son Kuo | 2002-07-09 |
| 6358796 | Method to fabricate a non-smiling effect structure in split-gate flash with self-aligned isolation | Yai-Fen Lin, Chia-Ta Hsieh, Hung-Cheng Sung, Juang-Ke Yeh | 2002-03-19 |
| 6117732 | Use of a metal contact structure to increase control gate coupling capacitance for a single polysilicon non-volatile memory cell | Wen-Ting Chu, Chuan-Li Chang, Ming-Chou Ho, Di-Son Kuo | 2000-09-12 |
| 6110782 | Method to combine high voltage device and salicide process | Wen-Ting Chu, Chuan-Li Chang, Ming-Chon Ho, Di-Son Kwo | 2000-08-29 |
| 6090668 | Method to fabricate sharp tip of poly in split gate flash | Yai-Fen Lin, Chia-Ta Hsieh, Hung-Cheng Sung, Jung-Ke Yeh, Di-Son Kuo | 2000-07-18 |
| 5872042 | Method for alignment mark regeneration | Shun-Liang Hsu, Syun-Ming Jang | 1999-02-16 |
| 5747382 | Two-step planarization process using chemical-mechanical polishing and reactive-ion-etching | Yung-Sheng Huang, Long-Sheng Yeou, Ji-Chung Huang | 1998-05-05 |